From: Alex Deucher <alexander.deucher@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: Alex Deucher <alexander.deucher@amd.com>
Subject: [PATCH 00/73] MES support
Date: Fri, 29 Apr 2022 13:44:23 -0400 [thread overview]
Message-ID: <20220429174536.459313-1-alexander.deucher@amd.com> (raw)
This patch set enables support for MES (Micro Engine Scheduler). This
is similar the the HWS (HardWare Scheduler) on the MEC currently used
for KFD. It's a scheduling microcontroller used for scheduling
engine queues to hardware slots. This adds the basic infrastructure
to enable MES in amdgpu.
Jack Xiao (70):
drm/amdgpu: define MQD abstract layer for hw ip
drm/amdgpu: add helper function to initialize mqd from ring v4
drm/amdgpu: add the per-context meta data v3
drm/amdgpu: add mes ctx data in amdgpu_ring
drm/amdgpu: define ring structure to access rptr/wptr/fence
drm/amdgpu: use ring structure to access rptr/wptr v2
drm/amdgpu: initialize/finalize the ring for mes queue
drm/amdgpu: assign the cpu/gpu address of fence from ring
drm/amdgpu/gfx10: implement mqd functions of gfx/compute eng v2
drm/amdgpu/gfx10: use per ctx CSA for ce metadata
drm/amdgpu/gfx10: use per ctx CSA for de metadata
drm/amdgpu/gfx10: associate mes queue id with fence v2
drm/amdgpu/gfx10: inherit vmid from mqd
drm/amdgpu/gfx10: use INVALIDATE_TLBS to invalidate TLBs v2
drm/amdgpu/gmc10: skip emitting pasid mapping packet
drm/amdgpu: use the whole doorbell space for mes
drm/amdgpu: update mes process/gang/queue definitions
drm/amdgpu: add mes_kiq module parameter v2
drm/amdgpu: allocate doorbell index for mes kiq
drm/amdgpu/mes: extend mes framework to support multiple mes pipes
drm/amdgpu/gfx10: add mes queue fence handling
drm/amdgpu/gfx10: add mes support for gfx ib test
drm/amdgpu: don't use kiq to flush gpu tlb if mes enabled
drm/amdgpu/sdma: use per-ctx sdma csa address for mes sdma queue
drm/amdgpu/sdma5.2: initialize sdma mqd
drm/amdgpu/sdma5.2: associate mes queue id with fence
drm/amdgpu/sdma5.2: add mes queue fence handling
drm/amdgpu/sdma5.2: add mes support for sdma ring test
drm/amdgpu/sdma5.2: add mes support for sdma ib test
drm/amdgpu/sdma5: initialize sdma mqd
drm/amdgpu/sdma5: associate mes queue id with fence
drm/amdgpu/sdma5: add mes queue fence handling
drm/amdgpu/sdma5: add mes support for sdma ring test
drm/amdgpu/sdma5: add mes support for sdma ib test
drm/amdgpu/mes: add mes kiq callback
drm/amdgpu: add mes kiq frontdoor loading support
drm/amdgpu: enable mes kiq N-1 test on sienna cichlid
drm/amdgpu/mes: manage mes doorbell allocation
drm/amdgpu: add mes queue id mask v2
drm/amdgpu/mes: initialize/finalize common mes structure v2
drm/amdgpu/mes: relocate status_fence slot allocation
drm/amdgpu/mes10.1: call general mes initialization
drm/amdgpu/mes10.1: add delay after mes engine enable
drm/amdgpu/mes10.1: implement the suspend/resume routine
drm/amdgpu/mes: implement creating mes process v2
drm/amdgpu/mes: implement destroying mes process
drm/amdgpu/mes: implement adding mes gang
drm/amdgpu/mes: implement removing mes gang
drm/amdgpu/mes: implement suspending all gangs
drm/amdgpu/mes: implement resuming all gangs
drm/amdgpu/mes: initialize mqd from queue properties
drm/amdgpu/mes: implement adding mes queue
drm/amdgpu/mes: implement removing mes queue
drm/amdgpu/mes: add helper function to convert ring to queue property
drm/amdgpu/mes: add helper function to get the ctx meta data offset
drm/amdgpu/mes: use ring for kernel queue submission
drm/amdgpu/mes: implement removing mes ring
drm/amdgpu/mes: add helper functions to alloc/free ctx metadata
drm/amdgpu: skip kfd routines when mes enabled
drm/amdgpu: skip some checking for mes queue ib submission
drm/amdgpu: skip kiq ib tests if mes enabled
drm/amdgpu: skip gds switch for mes queue
drm/amdgpu: kiq takes charge of all queues
drm/amdgpu/mes: map ctx metadata for mes self test
drm/amdgpu/mes: create gang and queues for mes self test
drm/amdgpu/mes: add ring/ib test for mes self test
drm/amdgpu/mes: implement mes self test
drm/amdgpu/mes10.1: add mes self test in late init
drm/amdgpu/mes: fix vm csa update issue
drm/amdgpu/mes: disable mes sdma queue test
Likun Gao (1):
drm/amdgpu: add mes kiq PSP GFX FW type
Mukul Joshi (2):
drm/amdgpu: Enable KFD with MES enabled
drm/amdgpu/mes: Update the doorbell function signatures
drivers/gpu/drm/amd/amdgpu/Makefile | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 24 +
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 42 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h | 6 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 10 +
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 4 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 3 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 8 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 1138 ++++++++++++++++++
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 168 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_mes_ctx.h | 121 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 6 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 193 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 22 +
drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c | 24 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 10 +
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 3 +-
drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 8 +-
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 383 +++---
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 8 +-
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 16 +-
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 20 +-
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 25 +-
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 6 +-
drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c | 4 +-
drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c | 4 +-
drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c | 4 +-
drivers/gpu/drm/amd/amdgpu/mes_v10_1.c | 461 ++++---
drivers/gpu/drm/amd/amdgpu/nv.c | 3 +-
drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 8 +-
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 16 +-
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 28 +-
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 169 ++-
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 171 ++-
drivers/gpu/drm/amd/amdgpu/si_dma.c | 4 +-
drivers/gpu/drm/amd/amdgpu/soc21.c | 3 +-
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 6 +-
drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 6 +-
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 12 +-
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 12 +-
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 12 +-
41 files changed, 2619 insertions(+), 553 deletions(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_mes_ctx.h
--
2.35.1
next reply other threads:[~2022-04-29 17:47 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-29 17:44 Alex Deucher [this message]
-- strict thread matches above, loose matches on Subject: below --
2022-04-29 17:45 [PATCH 00/73] MES support Alex Deucher
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20220429174536.459313-1-alexander.deucher@amd.com \
--to=alexander.deucher@amd.com \
--cc=amd-gfx@lists.freedesktop.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox