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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT068.mail.protection.outlook.com (10.13.173.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5206.12 via Frontend Transport; Fri, 29 Apr 2022 17:46:47 +0000 Received: from tr4.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.24; Fri, 29 Apr 2022 12:46:46 -0500 From: Alex Deucher To: Subject: [PATCH 17/73] drm/amdgpu: update mes process/gang/queue definitions Date: Fri, 29 Apr 2022 13:45:28 -0400 Message-ID: <20220429174624.459475-18-alexander.deucher@amd.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220429174624.459475-1-alexander.deucher@amd.com> References: <20220429174624.459475-1-alexander.deucher@amd.com> MIME-Version: 1.0 Content-Type: text/plain; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230001)(4636009)(40470700004)(46966006)(36840700001)(4326008)(8936002)(508600001)(8676002)(6916009)(54906003)(316002)(36860700001)(70206006)(70586007)(83380400001)(16526019)(15650500001)(66574015)(47076005)(36756003)(186003)(336012)(40460700003)(81166007)(2616005)(2906002)(1076003)(426003)(86362001)(5660300002)(7696005)(6666004)(26005)(82310400005)(356005)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Apr 2022 17:46:47.6439 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9f665ece-88b1-4bef-6c33-08da2a083bc7 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT068.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4113 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alex Deucher , Jack Xiao , =?UTF-8?q?Christian=20K=C3=B6nig?= , Hawking Zhang Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" From: Jack Xiao Update the definitions of MES process/gang/queue. v2: add missing includes Signed-off-by: Jack Xiao Acked-by: Christian König Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 58 +++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h index 7334982ea702..52483d7ce843 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h @@ -24,6 +24,10 @@ #ifndef __AMDGPU_MES_H__ #define __AMDGPU_MES_H__ +#include "amdgpu_irq.h" +#include "kgd_kfd_interface.h" +#include "amdgpu_gfx.h" + #define AMDGPU_MES_MAX_COMPUTE_PIPES 8 #define AMDGPU_MES_MAX_GFX_PIPES 2 #define AMDGPU_MES_MAX_SDMA_PIPES 2 @@ -37,11 +41,23 @@ enum amdgpu_mes_priority_level { AMDGPU_MES_PRIORITY_NUM_LEVELS }; +#define AMDGPU_MES_PROC_CTX_SIZE 0x1000 /* one page area */ +#define AMDGPU_MES_GANG_CTX_SIZE 0x1000 /* one page area */ + struct amdgpu_mes_funcs; struct amdgpu_mes { struct amdgpu_device *adev; + struct mutex mutex; + + struct idr pasid_idr; + struct idr gang_id_idr; + struct idr queue_id_idr; + struct ida doorbell_ida; + + spinlock_t queue_id_lock; + uint32_t total_max_queue; uint32_t doorbell_id_offset; uint32_t max_doorbell_slices; @@ -90,6 +106,48 @@ struct amdgpu_mes { const struct amdgpu_mes_funcs *funcs; }; +struct amdgpu_mes_process { + int pasid; + struct amdgpu_vm *vm; + uint64_t pd_gpu_addr; + struct amdgpu_bo *proc_ctx_bo; + uint64_t proc_ctx_gpu_addr; + void *proc_ctx_cpu_ptr; + uint64_t process_quantum; + struct list_head gang_list; + uint32_t doorbell_index; + unsigned long *doorbell_bitmap; + struct mutex doorbell_lock; +}; + +struct amdgpu_mes_gang { + int gang_id; + int priority; + int inprocess_gang_priority; + int global_priority_level; + struct list_head list; + struct amdgpu_mes_process *process; + struct amdgpu_bo *gang_ctx_bo; + uint64_t gang_ctx_gpu_addr; + void *gang_ctx_cpu_ptr; + uint64_t gang_quantum; + struct list_head queue_list; +}; + +struct amdgpu_mes_queue { + struct list_head list; + struct amdgpu_mes_gang *gang; + int queue_id; + uint64_t doorbell_off; + struct amdgpu_bo *mqd_obj; + void *mqd_cpu_ptr; + uint64_t mqd_gpu_addr; + uint64_t wptr_gpu_addr; + int queue_type; + int paging; + struct amdgpu_ring *ring; +}; + struct mes_add_queue_input { uint32_t process_id; uint64_t page_table_base_addr; -- 2.35.1