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Tue, 10 May 2022 15:45:34 -0500 From: David Zhang To: Subject: [PATCH v2 04/19] drm/amd/display: update GSP1 generic info packet for PSRSU Date: Tue, 10 May 2022 16:44:53 -0400 Message-ID: <20220510204508.506089-5-dingchen.zhang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220510204508.506089-1-dingchen.zhang@amd.com> References: <20220510204508.506089-1-dingchen.zhang@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 1cfcb697-81bf-48ac-8a76-08da32c60b1b X-MS-TrafficTypeDiagnostic: MWHPR12MB1629:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Uv7pLZ3rQjPvVZ3IZ2kl5lBiZ8ZOvOypFEheAsTO2MsvTsz/Yhe2+Mgh8QqgUo5d4B8wt6VAu/7jawmPW1w1wIUIgfhIoCCQXh8k8WOSJ0C0BobCs5tuOoX3/VhziIrDOXihm5eEoIOpNIlSSR943GPUkmRl23Qy9b1s3QHVkJduZpON0tKbNgSgVXRjUDBpnW3dJon/mtqqZ9DcqI4jrXfKuT00drv8SkVPYu3ZEzckDXlDMWarafW2EegNLIQr924TwSJecD39M7P452zKQ4k6CzEt9/k4OgKy+qU/2Ep4S/h6l+0EUNw9YsaUEWJmeizSW/VPgOIqIEx4iIogmIiDGk6mMQeVKJ9F5Qt//7Lm8e/AUILmSCf5Ju8z1eLUBWtdDiO6ErTgcTeBTWCH4WNNzAlEG1T/diEj9Y/TgDaWywOe76NJthqRFhLOIyVwza9/Yyw5Ogrwq++3/F1KHo06Q7KmkBFb3QRWPejtxQp/mPABGFbnJwleekEW4W4Dee2tbZcH+8oRuy3WHkI18jCEd3ep9RnNfwW8kWZ9Pe3krcmSKIykJX16xblEdLv54QRrKYWiAnr73D5YuA0A/uB3GUN2xuPNv9bs10hNrcMm3CI8yLMQrmITRnSdzu42seyV56QLsAsthzWE1+gvQpM9JZdGYzjbexu02vkBawFnsPNLZrKxsqQJHZY5HkC+h7x4w/X5udBHZPS0momf+q+/EmNQXbGl6JUNU9NBDjY= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB03.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230001)(4636009)(40470700004)(36840700001)(46966006)(508600001)(36860700001)(6916009)(54906003)(40460700003)(356005)(81166007)(316002)(86362001)(83380400001)(26005)(4326008)(8676002)(70206006)(5660300002)(6666004)(186003)(36756003)(7696005)(336012)(2616005)(15650500001)(1076003)(82310400005)(2906002)(426003)(47076005)(8936002)(70586007)(41533002)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 May 2022 20:45:39.6832 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1cfcb697-81bf-48ac-8a76-08da32c60b1b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT037.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1629 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: stylon.wang@amd.com, David Zhang , Sunpeng.Li@amd.com, Harry.Wentland@amd.com, qingqing.zhuo@amd.com, Rodrigo.Siqueira@amd.com, roman.li@amd.com, solomon.chiu@amd.com, jerry.zuo@amd.com, Aurabindo.Pillai@amd.com, wayne.lin@amd.com, Bhawanpreet.Lakha@amd.com, agustin.gutierrez@amd.com, pavle.kotarac@amd.com Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" [why & how] Based on PSRSU specification, every selective update frame need to use two SDP to indicate the frame active range. So we occupy another GSP1 for PSRSU execution. Signed-off-by: David Zhang --- .../display/dc/dcn30/dcn30_dio_stream_encoder.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c index a04ca4a98392..e40f01b596ad 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c @@ -419,6 +419,21 @@ static void enc3_stream_encoder_update_dp_info_packets( &info_frame->vsc, true); } + /* TODO: VSC SDP at packetIndex 1 should be restricted only if PSR-SU on. + * There should have another Infopacket type (e.g. vsc_psrsu) for PSR_SU. + * In addition, currently the driver check the valid bit then update and + * send the corresponding Infopacket. For PSR-SU, the SDP only be sent + * while entering PSR-SU mode. So we need another parameter(e.g. send) + * in dc_info_packet to indicate which infopacket should be enabled by + * default here. + */ + if (info_frame->vsc.valid) { + enc->vpg->funcs->update_generic_info_packet( + enc->vpg, + 1, /* packetIndex */ + &info_frame->vsc, + true); + } if (info_frame->spd.valid) { enc->vpg->funcs->update_generic_info_packet( enc->vpg, -- 2.25.1