AMD-GFX Archive on lore.kernel.org
 help / color / mirror / Atom feed
From: Hamza Mahfooz <hamza.mahfooz@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: stylon.wang@amd.com, Mustapha Ghaddar <Mustapha.Ghaddar@amd.com>,
	Jun Lei <Jun.Lei@amd.com>,
	Sunpeng.Li@amd.com, Harry.Wentland@amd.com,
	qingqing.zhuo@amd.com, Rodrigo.Siqueira@amd.com,
	roman.li@amd.com,
	Meenakshikumar Somasundaram <Meenakshikumar.Somasundaram@amd.com>,
	solomon.chiu@amd.com, jerry.zuo@amd.com,
	Aurabindo.Pillai@amd.com, hamza.mahfooz@amd.com,
	wayne.lin@amd.com, Jimmy Kizito <Jimmy.Kizito@amd.com>,
	Bhawanpreet.Lakha@amd.com, agustin.gutierrez@amd.com,
	pavle.kotarac@amd.com
Subject: [PATCH 13/16] drm/amd/display: Avoid reading LTTPR caps in non-LTTPR mode.
Date: Fri, 3 Jun 2022 16:11:44 -0400	[thread overview]
Message-ID: <20220603201147.121817-14-hamza.mahfooz@amd.com> (raw)
In-Reply-To: <20220603201147.121817-1-hamza.mahfooz@amd.com>

From: Jimmy Kizito <Jimmy.Kizito@amd.com>

[Why]
LTTPR capable devices on the DisplayPort path may assume that
extended LTTPR AUX timeouts will be used after LTTPR capabilities
are read.

When DPTX operates in non-LTTPR mode, AUX timeouts are not
extended and this can result in AUX transactions timing out.

[How]
Use shared helper function to determine LTTPR mode and do not
read LTTPR capabilities in non-LTTPR mode.

Reviewed-by: Mustapha Ghaddar <Mustapha.Ghaddar@amd.com>
Reviewed-by: Meenakshikumar Somasundaram <Meenakshikumar.Somasundaram@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Jimmy Kizito <Jimmy.Kizito@amd.com>
---
 .../gpu/drm/amd/display/dc/core/dc_link_dp.c  | 44 +++++++++++++------
 1 file changed, 31 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 9b20f340c21f..b5b16340fd39 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -5134,16 +5134,13 @@ static bool dpcd_read_sink_ext_caps(struct dc_link *link)
 	return true;
 }
 
-bool dp_retrieve_lttpr_cap(struct dc_link *link)
+/* Logic to determine LTTPR mode */
+static void determine_lttpr_mode(struct dc_link *link)
 {
-	uint8_t lttpr_dpcd_data[8];
 	bool allow_lttpr_non_transparent_mode = 0;
 	bool vbios_lttpr_enable = link->dc->caps.vbios_lttpr_enable;
 	bool vbios_lttpr_interop = link->dc->caps.vbios_lttpr_aware;
-	enum dc_status status = DC_ERROR_UNEXPECTED;
-	bool is_lttpr_present = false;
 
-	memset(lttpr_dpcd_data, '\0', sizeof(lttpr_dpcd_data));
 
 	if ((link->dc->config.allow_lttpr_non_transparent_mode.bits.DP2_0 &&
 			link->dpcd_caps.channel_coding_cap.bits.DP_128b_132b_SUPPORTED)) {
@@ -5153,9 +5150,6 @@ bool dp_retrieve_lttpr_cap(struct dc_link *link)
 		allow_lttpr_non_transparent_mode = 1;
 	}
 
-	/*
-	 * Logic to determine LTTPR mode
-	 */
 	link->lttpr_mode = LTTPR_MODE_NON_LTTPR;
 	if (vbios_lttpr_enable && vbios_lttpr_interop)
 		link->lttpr_mode = LTTPR_MODE_NON_TRANSPARENT;
@@ -5177,6 +5171,18 @@ bool dp_retrieve_lttpr_cap(struct dc_link *link)
 	    link->dc->debug.dpia_debug.bits.force_non_lttpr)
 		link->lttpr_mode = LTTPR_MODE_NON_LTTPR;
 #endif
+}
+
+bool dp_retrieve_lttpr_cap(struct dc_link *link)
+{
+	uint8_t lttpr_dpcd_data[8];
+	enum dc_status status = DC_ERROR_UNEXPECTED;
+	bool is_lttpr_present = false;
+
+	memset(lttpr_dpcd_data, '\0', sizeof(lttpr_dpcd_data));
+
+	/* Logic to determine LTTPR mode*/
+	determine_lttpr_mode(link);
 
 	if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT || link->lttpr_mode == LTTPR_MODE_TRANSPARENT) {
 		/* By reading LTTPR capability, RX assumes that we will enable
@@ -5292,11 +5298,23 @@ static enum dc_status wa_try_to_wake_dprx(struct dc_link *link, uint64_t timeout
 	uint64_t time_taken_ms = 0;
 	enum dc_connection_type type = dc_connection_none;
 
-	status = core_link_read_dpcd(
-			link,
-			DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
-			&dpcd_data,
-			sizeof(dpcd_data));
+	determine_lttpr_mode(link);
+
+	/* Issue an AUX read to test DPRX responsiveness. If LTTPR is supported the first read is expected to
+	 * be to determine LTTPR capabilities. Otherwise trying to read power state should be an innocuous AUX read.
+	 */
+	if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT || link->lttpr_mode == LTTPR_MODE_TRANSPARENT)
+		status = core_link_read_dpcd(
+				link,
+				DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
+				&dpcd_data,
+				sizeof(dpcd_data));
+	else
+		status = core_link_read_dpcd(
+				link,
+				DP_SET_POWER,
+				&dpcd_data,
+				sizeof(dpcd_data));
 
 	if (status != DC_OK) {
 		DC_LOG_WARNING("%s: Read DPCD LTTPR_CAP failed - try to toggle DPCD SET_POWER for %lld ms.",
-- 
2.36.1


  parent reply	other threads:[~2022-06-03 20:12 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-06-03 20:11 [PATCH 00/16] DC Patches May 30, 2022 Hamza Mahfooz
2022-06-03 20:11 ` [PATCH 01/16] drm/amd/display: Update optimized blank calc and programming Hamza Mahfooz
2022-06-03 20:11 ` [PATCH 02/16] drm/amd/display: Detect dpcd_rev when hotplug mst monitor Hamza Mahfooz
2022-06-03 20:11 ` [PATCH 03/16] Revert "drm/amd/display: Pass the new context into disable OTG WA" Hamza Mahfooz
2022-06-03 20:11 ` [PATCH 04/16] drm/amd/display: Blank eDP on enable drv if odm enabled Hamza Mahfooz
2022-06-03 20:11 ` [PATCH 05/16] drm/amd/display: Correct min comp buffer size Hamza Mahfooz
2022-06-03 20:11 ` [PATCH 06/16] drm/amd/display: add DP sanity checks during enable stream Hamza Mahfooz
2022-06-03 20:11 ` [PATCH 07/16] drm/amd/display: Cap OLED brightness per max frame-average luminance Hamza Mahfooz
2022-06-08 10:02   ` Aaron Ma
2022-06-08 19:02     ` Li, Roman
2022-06-03 20:11 ` [PATCH 08/16] drm/amd/display: Enable 3 plane MPO Hamza Mahfooz
2022-06-03 20:11 ` [PATCH 09/16] drm/amd/display: [FW Promotion] Release 0.0.119.0 Hamza Mahfooz
2022-06-03 20:11 ` [PATCH 10/16] drm/amd/display: 3.2.188 Hamza Mahfooz
2022-06-03 20:11 ` [PATCH 11/16] drm/amd/display: Fix dpp dto for disabled pipes Hamza Mahfooz
2022-06-03 20:11 ` [PATCH 12/16] drm/amd/display: Fix entry into transient encoder assignment mode Hamza Mahfooz
2022-06-03 20:11 ` Hamza Mahfooz [this message]
2022-06-03 20:11 ` [PATCH 14/16] drm/amd/display: Extend soc BB capabilitiy Hamza Mahfooz
2022-06-03 20:11 ` [PATCH 15/16] drm/amd/display: Add HDMI member to DTO Hamza Mahfooz
2022-06-03 20:11 ` [PATCH 16/16] drm/amd/display: 3.2.189 Hamza Mahfooz
2022-06-06 13:38 ` [PATCH 00/16] DC Patches May 30, 2022 Wheeler, Daniel

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20220603201147.121817-14-hamza.mahfooz@amd.com \
    --to=hamza.mahfooz@amd.com \
    --cc=Aurabindo.Pillai@amd.com \
    --cc=Bhawanpreet.Lakha@amd.com \
    --cc=Harry.Wentland@amd.com \
    --cc=Jimmy.Kizito@amd.com \
    --cc=Jun.Lei@amd.com \
    --cc=Meenakshikumar.Somasundaram@amd.com \
    --cc=Mustapha.Ghaddar@amd.com \
    --cc=Rodrigo.Siqueira@amd.com \
    --cc=Sunpeng.Li@amd.com \
    --cc=agustin.gutierrez@amd.com \
    --cc=amd-gfx@lists.freedesktop.org \
    --cc=jerry.zuo@amd.com \
    --cc=pavle.kotarac@amd.com \
    --cc=qingqing.zhuo@amd.com \
    --cc=roman.li@amd.com \
    --cc=solomon.chiu@amd.com \
    --cc=stylon.wang@amd.com \
    --cc=wayne.lin@amd.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox