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SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230016)(4636009)(346002)(39860400002)(376002)(396003)(136003)(40470700004)(46966006)(36840700001)(1076003)(6666004)(478600001)(4326008)(2906002)(41300700001)(316002)(40460700003)(86362001)(186003)(16526019)(2616005)(8676002)(70586007)(8936002)(83380400001)(82310400005)(70206006)(36756003)(40480700001)(6916009)(47076005)(54906003)(81166007)(356005)(7696005)(82740400003)(36860700001)(336012)(26005)(5660300002)(426003)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jun 2022 19:13:49.1484 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2507aac2-f99a-414c-839e-08da5acca9a1 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT023.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1613 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: stylon.wang@amd.com, Sunpeng.Li@amd.com, Harry.Wentland@amd.com, qingqing.zhuo@amd.com, Rodrigo.Siqueira@amd.com, roman.li@amd.com, Daniel Wheeler , solomon.chiu@amd.com, jerry.zuo@amd.com, Aurabindo.Pillai@amd.com, hamza.mahfooz@amd.com, wayne.lin@amd.com, Bhawanpreet.Lakha@amd.com, agustin.gutierrez@amd.com, pavle.kotarac@amd.com Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" This DC patchset is a large one that brings improvements in multiple areas. In summary, we highlight: - Program ACP-related registers - Fixes for DMUB, DPIA, PSR, and others - Improvements in the pipe split - Add SubVP code - Add basic setup for FAMS support - Improve BB capabilities Cc: Daniel Wheeler Thanks Siqueira Alan Liu (1): drm/amd/display: Program ACP related register Alvin Lee (5): drm/amd/display: Add SubVP required code drm/amd/display: Change DET policy for MPO cases drm/amd/display: Make OPTC3 function accessible to other DCN drm/amd/display: Don't set dram clock change requirement for SubVP drm/amd/display: Maintain old audio programming sequence Aric Cyr (1): drm/amd/display: 3.2.192 Chris Park (3): drm/amd/display: Switch to correct DTO on HDMI drm/amd/display: Indicate stream change on ODM change drm/amd/display: OVT Update on InfoFrame and Mode Management Dmytro Laktyushkin (2): drm/amd/display: disable timing sync b/w odm halves drm/amd/display: disable otg toggle w/a on boot Duncan Ma (1): drm/amd/display: Add flag to modify MST delay Eric Bernstein (3): drm/amd/display: Add function to set pixels per cycle drm/amd/display: Update gpuvm_max_page_table_levels IP param drm/amd/display: Fix null timing generator resource Evgenii Krasnikov (1): drm/amd/display: add an option to skip wait for HPD when powering on eDP panel Fangzhi Zuo (1): drm/amd/display: Fix dmub soft hang for PSR 1 Hamza Mahfooz (2): drm/amd/display: enable PCON SST support for newer ASICs drm/amd/display: rename hdmi_frl_pcon_support Harry Wentland (1): drm/amd/display: Move all linux includes into OS types Jimmy Kizito (3): drm/amd/display: Maintain consistent mode of operation during encoder assignment drm/amd/display: Disable TBT3 DSC work around by default. drm/amd/display: Fix uninitialized variable. Jun Lei (1): drm/amd/display: Extend soc BB capabilitiy Martin Leung (2): drm/amd/display: Prepare for new interfaces drm/amd/display: guard for virtual calling destroy_link_encoders Meenakshikumar Somasundaram (1): drm/amd/display: Remove configuration option for dpia hpd delay Michael Strauss (1): drm/amd/display: Initialize lt_settings on instantiation Nicholas Kazlauskas (4): drm/amd/display: Fix stream->link_enc unassigned during stream removal drm/amd/display: Guard against ddc_pin being NULL for AUX drm/amd/display: Remove incorrect ASSERT check for link_enc drm/amd/display: Guard against NULL link encoder in log hw state Rodrigo Siqueira (6): drm/amd/display: Add missing registers for ACP drm/amd/display: Use two pixel per container for k1/k2 div drm/amd/display: Add basic infrastructure for enabling FAMS drm/amd/display: Add SubVP control lock drm/amd/display: Add minimal pipe split transition state drm/amd/display: Fix refresh rate issue on Club 3D Samson Tam (1): drm/amd/display: Apply ODM 2:1 policy for single display configuration .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 10 +- drivers/gpu/drm/amd/display/dc/Makefile | 27 +- .../gpu/drm/amd/display/dc/basics/vector.c | 2 - .../drm/amd/display/dc/bios/bios_parser2.c | 2 - .../gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 6 + .../dc/clk_mgr/dcn315/dcn315_clk_mgr.c | 7 +- .../display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 2 + .../dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c | 5 +- drivers/gpu/drm/amd/display/dc/core/dc.c | 384 +++++++++- .../drm/amd/display/dc/core/dc_hw_sequencer.c | 2 - .../gpu/drm/amd/display/dc/core/dc_link_ddc.c | 2 - .../gpu/drm/amd/display/dc/core/dc_link_dp.c | 9 +- .../drm/amd/display/dc/core/dc_link_dpia.c | 58 +- .../drm/amd/display/dc/core/dc_link_enc_cfg.c | 32 + .../gpu/drm/amd/display/dc/core/dc_resource.c | 32 +- drivers/gpu/drm/amd/display/dc/core/dc_sink.c | 2 - .../gpu/drm/amd/display/dc/core/dc_stream.c | 3 - .../gpu/drm/amd/display/dc/core/dc_surface.c | 2 - drivers/gpu/drm/amd/display/dc/dc.h | 27 +- drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 416 +++++++++++ drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h | 4 + drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 2 + drivers/gpu/drm/amd/display/dc/dc_stream.h | 24 +- drivers/gpu/drm/amd/display/dc/dc_types.h | 5 + .../gpu/drm/amd/display/dc/dce/dce_audio.c | 13 +- drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 8 +- .../drm/amd/display/dc/dce/dce_clock_source.c | 2 - drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c | 3 - .../gpu/drm/amd/display/dc/dce/dce_i2c_sw.c | 2 - drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c | 2 - .../drm/amd/display/dc/dce/dce_link_encoder.c | 3 - drivers/gpu/drm/amd/display/dc/dce/dce_opp.c | 2 - .../amd/display/dc/dce/dce_stream_encoder.c | 5 +- .../amd/display/dc/dce/dce_stream_encoder.h | 14 +- .../amd/display/dc/dce100/dce100_resource.c | 2 - .../amd/display/dc/dce110/dce110_compressor.c | 3 - .../display/dc/dce110/dce110_hw_sequencer.c | 10 +- .../display/dc/dce110/dce110_opp_regamma_v.c | 2 - .../amd/display/dc/dce110/dce110_resource.c | 2 - .../display/dc/dce110/dce110_transform_v.c | 2 - .../amd/display/dc/dce112/dce112_compressor.c | 3 - .../amd/display/dc/dce112/dce112_resource.c | 2 - .../amd/display/dc/dce120/dce120_resource.c | 2 - .../drm/amd/display/dc/dce80/dce80_resource.c | 2 - .../drm/amd/display/dc/dcn10/dcn10_hubbub.c | 2 - .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 2 +- .../gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c | 2 - .../amd/display/dc/dcn10/dcn10_link_encoder.c | 3 - .../gpu/drm/amd/display/dc/dcn10/dcn10_opp.c | 2 - .../drm/amd/display/dc/dcn10/dcn10_resource.c | 2 - .../display/dc/dcn10/dcn10_stream_encoder.c | 5 +- .../display/dc/dcn10/dcn10_stream_encoder.h | 17 +- .../drm/amd/display/dc/dcn20/dcn20_hwseq.c | 44 +- .../drm/amd/display/dc/dcn20/dcn20_resource.c | 12 +- .../display/dc/dcn20/dcn20_stream_encoder.c | 1 - .../drm/amd/display/dc/dcn21/dcn21_resource.c | 2 +- .../dc/dcn30/dcn30_dio_stream_encoder.c | 4 +- .../dc/dcn30/dcn30_dio_stream_encoder.h | 6 +- .../drm/amd/display/dc/dcn30/dcn30_hwseq.c | 22 +- .../gpu/drm/amd/display/dc/dcn30/dcn30_mpc.h | 106 ++- .../gpu/drm/amd/display/dc/dcn30/dcn30_optc.c | 5 + .../drm/amd/display/dc/dcn30/dcn30_resource.c | 172 ++++- .../drm/amd/display/dc/dcn31/dcn31_resource.c | 2 +- .../amd/display/dc/dcn315/dcn315_resource.c | 1 + .../amd/display/dc/dcn316/dcn316_resource.c | 1 + drivers/gpu/drm/amd/display/dc/dcn32/Makefile | 14 +- .../gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c | 4 + .../dc/dcn32/dcn32_dio_stream_encoder.c | 8 +- .../dc/dcn32/dcn32_dio_stream_encoder.h | 1 + .../drm/amd/display/dc/dcn32/dcn32_hwseq.c | 245 ++++++- .../drm/amd/display/dc/dcn32/dcn32_hwseq.h | 21 + .../gpu/drm/amd/display/dc/dcn32/dcn32_init.c | 12 +- .../gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c | 236 +++++- .../gpu/drm/amd/display/dc/dcn32/dcn32_mpc.h | 117 ++- .../gpu/drm/amd/display/dc/dcn32/dcn32_optc.c | 2 +- .../drm/amd/display/dc/dcn32/dcn32_resource.c | 680 +++++++++++++----- .../drm/amd/display/dc/dcn32/dcn32_resource.h | 20 +- .../display/dc/dcn32/dcn32_resource_helpers.c | 260 +++++++ .../amd/display/dc/dcn321/dcn321_resource.c | 522 ++++++++++---- .../drm/amd/display/dc/dml/dcn20/dcn20_fpu.c | 6 + .../drm/amd/display/dc/dml/dcn30/dcn30_fpu.c | 2 + .../amd/display/dc/dml/display_mode_structs.h | 3 + .../drm/amd/display/dc/dml/display_mode_vba.c | 5 +- .../gpu/drm/amd/display/dc/gpio/gpio_base.c | 2 - .../drm/amd/display/dc/gpio/gpio_service.c | 2 - drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c | 3 - .../gpu/drm/amd/display/dc/gpio/hw_factory.c | 2 - drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c | 2 - .../gpu/drm/amd/display/dc/inc/core_types.h | 5 +- .../gpu/drm/amd/display/dc/inc/dc_link_dp.h | 6 +- .../amd/display/dc/inc/hw/stream_encoder.h | 1 + .../gpu/drm/amd/display/dc/inc/hw_sequencer.h | 7 + .../amd/display/dc/inc/hw_sequencer_private.h | 2 + .../gpu/drm/amd/display/dc/inc/link_enc_cfg.h | 5 + .../dc/irq/dce110/irq_service_dce110.c | 2 - .../dc/irq/dce120/irq_service_dce120.c | 2 - .../display/dc/irq/dce80/irq_service_dce80.c | 2 - .../display/dc/irq/dcn10/irq_service_dcn10.c | 2 - .../gpu/drm/amd/display/dc/irq/irq_service.c | 2 - drivers/gpu/drm/amd/display/dc/os_types.h | 5 +- .../display/dc/virtual/virtual_link_encoder.c | 2 - .../dc/virtual/virtual_stream_encoder.c | 2 - .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 114 ++- .../amd/display/dmub/inc/dmub_subvp_state.h | 160 +++++ .../drm/amd/display/include/set_mode_types.h | 8 +- .../amd/display/modules/color/color_gamma.c | 3 - .../amd/display/modules/freesync/freesync.c | 2 - .../include/asic_reg/dce/dce_6_0_sh_mask.h | 2 + .../include/asic_reg/dcn/dcn_3_0_0_sh_mask.h | 2 + .../include/asic_reg/dcn/dcn_3_0_1_sh_mask.h | 2 + .../include/asic_reg/dcn/dcn_3_0_2_sh_mask.h | 2 + .../include/asic_reg/dcn/dcn_3_0_3_sh_mask.h | 2 + .../include/asic_reg/dcn/dcn_3_1_2_sh_mask.h | 2 + 113 files changed, 3502 insertions(+), 573 deletions(-) create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c create mode 100644 drivers/gpu/drm/amd/display/dmub/inc/dmub_subvp_state.h -- 2.25.1