From: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: stylon.wang@amd.com, Sunpeng.Li@amd.com, Harry.Wentland@amd.com,
qingqing.zhuo@amd.com, Rodrigo.Siqueira@amd.com,
roman.li@amd.com, solomon.chiu@amd.com, jerry.zuo@amd.com,
Aurabindo.Pillai@amd.com, hamza.mahfooz@amd.com,
wayne.lin@amd.com, Bhawanpreet.Lakha@amd.com,
agustin.gutierrez@amd.com, pavle.kotarac@amd.com
Subject: [PATCH 01/40] drm/amd/display: Add missing registers for ACP
Date: Thu, 30 Jun 2022 15:12:43 -0400 [thread overview]
Message-ID: <20220630191322.909650-2-Rodrigo.Siqueira@amd.com> (raw)
In-Reply-To: <20220630191322.909650-1-Rodrigo.Siqueira@amd.com>
We are missing some ACP registers/mask value for some specific ASICs.
This commit includes it to those ASICs that support it.
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_sh_mask.h | 2 ++
drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_1_sh_mask.h | 2 ++
drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_2_sh_mask.h | 2 ++
drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_sh_mask.h | 2 ++
drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_sh_mask.h | 2 ++
5 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_sh_mask.h
index ea683f452bb3..b79be3a25a80 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_sh_mask.h
@@ -38746,12 +38746,14 @@
#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5
#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8
#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND__SHIFT 0xc
#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10
#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L
#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L
#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L
#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L
#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND_MASK 0x00001000L
#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L
//DIG0_HDMI_INFOFRAME_CONTROL0
#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_1_sh_mask.h
index 59155007c186..e454d4469f17 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_1_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_1_sh_mask.h
@@ -29361,12 +29361,14 @@
#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5
#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8
#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND__SHIFT 0xc
#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10
#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L
#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L
#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L
#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L
#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND_MASK 0x00001000L
#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L
//DIG0_HDMI_INFOFRAME_CONTROL0
#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_2_sh_mask.h
index 396c33fafc91..b9de0ebc8b03 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_2_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_2_sh_mask.h
@@ -33955,12 +33955,14 @@
#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5
#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8
#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND__SHIFT 0xc
#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10
#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L
#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L
#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L
#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L
#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND_MASK 0x00001000L
#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L
//DIG0_HDMI_INFOFRAME_CONTROL0
#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_sh_mask.h
index e8f4ad05932b..5c469cf635e5 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_sh_mask.h
@@ -18093,12 +18093,14 @@
#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5
#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8
#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND__SHIFT 0xc
#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10
#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L
#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L
#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L
#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L
#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND_MASK 0x00001000L
#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L
//DIG0_HDMI_INFOFRAME_CONTROL0
#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_sh_mask.h
index 1f21f313bd1d..cf3398f15666 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_sh_mask.h
@@ -33961,12 +33961,14 @@
#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5
#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8
#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND__SHIFT 0xc
#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10
#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L
#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L
#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L
#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L
#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND_MASK 0x00001000L
#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L
//DIG0_HDMI_INFOFRAME_CONTROL0
#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4
--
2.25.1
next prev parent reply other threads:[~2022-06-30 19:13 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-30 19:12 [PATCH 00/40] DC Patches Jun 30, 2022 Rodrigo Siqueira
2022-06-30 19:12 ` Rodrigo Siqueira [this message]
2022-06-30 19:12 ` [PATCH 02/40] drm/amd/display: Add SubVP required code Rodrigo Siqueira
2022-07-06 17:58 ` Nathan Chancellor
2022-07-06 19:38 ` Alex Deucher
2022-07-06 20:30 ` Nathan Chancellor
2022-06-30 19:12 ` [PATCH 03/40] drm/amd/display: Prepare for new interfaces Rodrigo Siqueira
2022-06-30 19:12 ` [PATCH 04/40] drm/amd/display: Add function to set pixels per cycle Rodrigo Siqueira
2022-06-30 19:12 ` [PATCH 05/40] drm/amd/display: Apply ODM 2:1 policy for single display configuration Rodrigo Siqueira
2022-06-30 19:12 ` [PATCH 06/40] drm/amd/display: Use two pixel per container for k1/k2 div Rodrigo Siqueira
2022-06-30 19:12 ` [PATCH 07/40] drm/amd/display: Change DET policy for MPO cases Rodrigo Siqueira
2022-06-30 19:12 ` [PATCH 08/40] drm/amd/display: Switch to correct DTO on HDMI Rodrigo Siqueira
2022-06-30 19:12 ` [PATCH 09/40] drm/amd/display: Update gpuvm_max_page_table_levels IP param Rodrigo Siqueira
2022-06-30 19:12 ` [PATCH 10/40] drm/amd/display: Make OPTC3 function accessible to other DCN Rodrigo Siqueira
2022-06-30 19:12 ` [PATCH 11/40] drm/amd/display: Add basic infrastructure for enabling FAMS Rodrigo Siqueira
2022-06-30 19:12 ` [PATCH 12/40] drm/amd/display: Fix stream->link_enc unassigned during stream removal Rodrigo Siqueira
2022-06-30 19:12 ` [PATCH 13/40] drm/amd/display: Add SubVP control lock Rodrigo Siqueira
2022-06-30 19:12 ` [PATCH 14/40] drm/amd/display: Add minimal pipe split transition state Rodrigo Siqueira
2022-06-30 19:12 ` [PATCH 15/40] drm/amd/display: disable timing sync b/w odm halves Rodrigo Siqueira
2022-06-30 19:12 ` [PATCH 16/40] drm/amd/display: guard for virtual calling destroy_link_encoders Rodrigo Siqueira
2022-06-30 19:12 ` [PATCH 17/40] drm/amd/display: Maintain consistent mode of operation during encoder assignment Rodrigo Siqueira
2022-06-30 19:13 ` [PATCH 18/40] drm/amd/display: Extend soc BB capabilitiy Rodrigo Siqueira
2022-06-30 19:13 ` [PATCH 19/40] drm/amd/display: Don't set dram clock change requirement for SubVP Rodrigo Siqueira
2022-06-30 19:13 ` [PATCH 20/40] drm/amd/display: add an option to skip wait for HPD when powering on eDP panel Rodrigo Siqueira
2022-06-30 19:13 ` [PATCH 21/40] drm/amd/display: Program ACP related register Rodrigo Siqueira
2022-06-30 19:13 ` [PATCH 22/40] drm/amd/display: Guard against ddc_pin being NULL for AUX Rodrigo Siqueira
2022-06-30 19:13 ` [PATCH 23/40] drm/amd/display: Remove incorrect ASSERT check for link_enc Rodrigo Siqueira
2022-06-30 19:13 ` [PATCH 24/40] drm/amd/display: Guard against NULL link encoder in log hw state Rodrigo Siqueira
2022-06-30 19:13 ` [PATCH 25/40] drm/amd/display: Fix dmub soft hang for PSR 1 Rodrigo Siqueira
2022-06-30 19:13 ` [PATCH 26/40] drm/amd/display: disable otg toggle w/a on boot Rodrigo Siqueira
2022-06-30 19:13 ` [PATCH 27/40] drm/amd/display: Indicate stream change on ODM change Rodrigo Siqueira
2022-06-30 19:13 ` [PATCH 28/40] drm/amd/display: Remove configuration option for dpia hpd delay Rodrigo Siqueira
2022-06-30 19:13 ` [PATCH 29/40] drm/amd/display: Fix refresh rate issue on Club 3D Rodrigo Siqueira
2022-06-30 19:13 ` [PATCH 30/40] drm/amd/display: Disable TBT3 DSC work around by default Rodrigo Siqueira
2022-06-30 19:13 ` [PATCH 31/40] drm/amd/display: Add flag to modify MST delay Rodrigo Siqueira
2022-06-30 19:13 ` [PATCH 32/40] drm/amd/display: Fix null timing generator resource Rodrigo Siqueira
2022-06-30 19:13 ` [PATCH 33/40] drm/amd/display: Move all linux includes into OS types Rodrigo Siqueira
2022-06-30 19:13 ` [PATCH 34/40] drm/amd/display: Fix uninitialized variable Rodrigo Siqueira
2022-06-30 19:13 ` [PATCH 35/40] drm/amd/display: Initialize lt_settings on instantiation Rodrigo Siqueira
2022-06-30 19:13 ` [PATCH 36/40] drm/amd/display: OVT Update on InfoFrame and Mode Management Rodrigo Siqueira
2022-06-30 19:13 ` [PATCH 37/40] drm/amd/display: enable PCON SST support for newer ASICs Rodrigo Siqueira
2022-06-30 19:13 ` [PATCH 38/40] drm/amd/display: rename hdmi_frl_pcon_support Rodrigo Siqueira
2022-06-30 19:13 ` [PATCH 39/40] drm/amd/display: Maintain old audio programming sequence Rodrigo Siqueira
2022-06-30 19:13 ` [PATCH 40/40] drm/amd/display: 3.2.192 Rodrigo Siqueira
2022-07-05 13:16 ` [PATCH 00/40] DC Patches Jun 30, 2022 Wheeler, Daniel
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