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Fri, 26 Aug 2022 21:26:37 -0500 From: brichang To: Subject: [PATCH 01/33] drm/amd/display: Set ODM policy based on number of DSC slices Date: Sat, 27 Aug 2022 06:26:50 +0800 Message-ID: <20220826222722.1428063-2-Brian.Chang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220826222722.1428063-1-Brian.Chang@amd.com> References: <20220826222722.1428063-1-Brian.Chang@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: c51becff-a019-4d9e-3860-08da87d394bd X-MS-TrafficTypeDiagnostic: MW3PR12MB4443:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: g/YcjDM53DbU9HKT9aYs/HRsq7w55CePuQshtAr6YUiMJ0lan4sEoKgLJj10WVdNjhZ9GEophwZr9dp/1nE7Ra1rHuo4zknO6zChdY0wp3TtdiVv1O8bPRTIvdl7ImVE7IdqXHQWzxXv8YwCoGX2xdlyC+jEf+h8Amjl92i7KiOP0RlYaKzzXV94kskypYtugBq6sTlcX8J6M/aG6G2AFwOhcpomEQ4uWTaB2SJPtIhvXee5pevF42TKPZgc0zJLHGZOZzoypF3hftbfLGMMa54fRKGaQ9diCuWDH2LmTELrtiJ3hIXikd69Ra2OHEXtDjTPfn4la30J+G3HqclqWIOPEjVw55EYCmZawyY89q6+j3RVoN0ZOFMn6jPjkORkkeCM9GL+vNccHbQO6+zANs2H2gb5PZS7qVhUunIRM1K+j24ujjWNgcO7TAUEaCeAod11FxqFEPQBjIjgDSrsvPbEsoiXkT6Rzk9Qf8B78O2163cpt41UC1H587FCeBVnvbzzjvPzaTygzoK2FiyusSqrJ1nr8IqxyGQa5RBW/D8BEDu7dDud8DKQJ2kX+biQDvHSmpWHbJIV7V7kt77e4qDyMlzvYYc1YiU4YJkVzfKz9uZmHXxG70Dgg5lcQw0F39FrAwRXOJ9AA9ThAkJSdmjPHghsH5you+W7c83ndkW9rm4mK6QRRjxLBDgzFkGe36Qrvh+G57SOiepr4gYG+1suoJnvxz+4ntLyTOSBLpKbYjcMbqEb+19NOt8rkQOKs0YeYSIWW7hCsb7v0GcjmUCldJoAYhknKbBzJQ7nTtp5Hwrl0RWowHdMWjLm5fB9ue1m0KnVv1GTb01C+8P3uQ== X-Forefront-Antispam-Report: CIP:165.204.84.17; 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Reviewed-by: Alvin Lee Acked-by: Brian Chang Signed-off-by: Taimur Hassan --- .../gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c | 2 ++ .../amd/display/dc/dml/dcn32/display_mode_vba_util_32.c | 7 +++++-- .../amd/display/dc/dml/dcn32/display_mode_vba_util_32.h | 1 + 3 files changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c index cb2025771646..f831855db022 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c @@ -2045,6 +2045,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading, mode_lib->vba.DISPCLKRampingMargin, mode_lib->vba.DISPCLKDPPCLKVCOSpeed, + mode_lib->vba.NumberOfDSCSlices[k], /* Output */ &v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.TotalAvailablePipesSupportNoDSC, @@ -2066,6 +2067,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading, mode_lib->vba.DISPCLKRampingMargin, mode_lib->vba.DISPCLKDPPCLKVCOSpeed, + mode_lib->vba.NumberOfDSCSlices[k], /* Output */ &v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.TotalAvailablePipesSupportDSC, diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c index 05fc14a47fba..6b3c4dbb140b 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c @@ -1193,6 +1193,7 @@ void dml32_CalculateODMMode( double DISPCLKDPPCLKDSCCLKDownSpreading, double DISPCLKRampingMargin, double DISPCLKDPPCLKVCOSpeed, + unsigned int NumberOfDSCSlices, /* Output */ bool *TotalAvailablePipesSupport, @@ -1228,7 +1229,8 @@ void dml32_CalculateODMMode( if (!(Output == dm_hdmi || Output == dm_dp || Output == dm_edp) && (ODMUse == dm_odm_combine_policy_4to1 || ((SurfaceRequiredDISPCLKWithODMCombineTwoToOne > StateDispclk || - (DSCEnable && (HActive > 2 * MaximumPixelsPerLinePerDSCUnit)))))) { + (DSCEnable && (HActive > 2 * MaximumPixelsPerLinePerDSCUnit)) + || NumberOfDSCSlices > 8)))) { if (TotalNumberOfActiveDPP + 4 <= MaxNumDPP) { *ODMMode = dm_odm_combine_mode_4to1; *RequiredDISPCLKPerSurface = SurfaceRequiredDISPCLKWithODMCombineFourToOne; @@ -1239,7 +1241,8 @@ void dml32_CalculateODMMode( } else if (Output != dm_hdmi && (ODMUse == dm_odm_combine_policy_2to1 || (((SurfaceRequiredDISPCLKWithoutODMCombine > StateDispclk && SurfaceRequiredDISPCLKWithODMCombineTwoToOne <= StateDispclk) || - (DSCEnable && (HActive > MaximumPixelsPerLinePerDSCUnit)))))) { + (DSCEnable && (HActive > MaximumPixelsPerLinePerDSCUnit)) + || (NumberOfDSCSlices <= 8 && NumberOfDSCSlices > 4))))) { if (TotalNumberOfActiveDPP + 2 <= MaxNumDPP) { *ODMMode = dm_odm_combine_mode_2to1; *RequiredDISPCLKPerSurface = SurfaceRequiredDISPCLKWithODMCombineTwoToOne; diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h index d293856ba906..626f6605e2d5 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h @@ -226,6 +226,7 @@ void dml32_CalculateODMMode( double DISPCLKDPPCLKDSCCLKDownSpreading, double DISPCLKRampingMargin, double DISPCLKDPPCLKVCOSpeed, + unsigned int NumberOfDSCSlices, /* Output */ bool *TotalAvailablePipesSupport, -- 2.25.1