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Fri, 26 Aug 2022 21:52:10 -0500 From: brichang To: Subject: [PATCH 24/33] drm/amd/display: Fix primary EDP link detection Date: Sat, 27 Aug 2022 06:50:44 +0800 Message-ID: <20220826225053.1435588-25-Brian.Chang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220826225053.1435588-1-Brian.Chang@amd.com> References: <20220826225053.1435588-1-Brian.Chang@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 3d377770-420c-4f68-25fb-08da87d72984 X-MS-TrafficTypeDiagnostic: CH0PR12MB5124:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Ibsmua6z3/8ht38MnXW1OmK17VZHEG7ZLO60LHFlalL43VTZck0aQL66hkI14rPhh1R273nQc+7xtgKKxqOXWUT6Yn19qaH7cZP3X2EOJM/fWPN4/5faAbzLVyNpLgErIUn8F8GmW6U6g1W524vKP0Ea+l6cTXBV9dXFF93u0PIa22MXyFHXZbPaepJNRobM07mmGMd/FbwbIgEyAdbwz3Hv6sPEujwVAeOjjlIyF/GVWqxEORo6l0YcsT93u6t5MbwmAebFVpOJW5/piXhWdiIufk/4zZ0Jb7jpBdkEZdfNLeQ6c0Xem1ZOp2JfYqLnJK+ojkqNG+z14WWppNHhUO96p44GjKk9mK85FT36iDuxTI8hz1Ht1fQibcdH76lOHSn9eti09ykfAwoz9C2IHblwfQe/eXu3OY1+NIxRX/NJu5LhCd7gazejbzPvtNsoM+/9w8XDtxmm9moD/h2pneNVA1NkTn7YqlsUN8rWkhvAStkX7L3nD4zzxzXLL/Q0VHmiykokYkMU3zo7Vefal7IGlau9vu49SaWiWFW5E9tUV+kbZ2xFApPW2GYcfitJ/AFhjHPxajRv79H4SyC11Cu87DspAKxLpojYeVOmwsF+reY/SLSdzABJHBDBrZ8zJhg5PJatV/y4cJOkx1X+ozdnLNPeS95I26u5esxqLzhxdbQpE1OzTSYsjIBuJHjG24eFwgmeS6uVM0KFL/InFWnNLIXeWES+JDJjzDgbA8sqyD3t4GIwhCSYQpJZFVHoSHjGVvlPYpuD13X9mXXIHFuQROTaKj/xuYbeXdbnqPCxigkiIdkCcUcCVbyhWg6mF0iARLMulSPG4+B2Ur8oXw== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230016)(4636009)(396003)(346002)(376002)(39860400002)(136003)(46966006)(36840700001)(40470700004)(6666004)(26005)(7696005)(41300700001)(426003)(47076005)(186003)(336012)(83380400001)(1076003)(2616005)(2906002)(8936002)(5660300002)(82310400005)(40460700003)(40480700001)(6916009)(54906003)(316002)(4326008)(8676002)(70206006)(70586007)(478600001)(356005)(81166007)(82740400003)(36756003)(86362001)(36860700001)(43062005)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Aug 2022 02:52:20.9653 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3d377770-420c-4f68-25fb-08da87d72984 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT017.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB5124 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: stylon.wang@amd.com, Brian Chang , Jayendran Ramani , Iswara Nagulendran , Sunpeng.Li@amd.com, Harry.Wentland@amd.com, qingqing.zhuo@amd.com, Rodrigo.Siqueira@amd.com, roman.li@amd.com, solomon.chiu@amd.com, Aurabindo.Pillai@amd.com, Harry Vanzylldejong , wayne.lin@amd.com, sregolui , Bhawanpreet.Lakha@amd.com, agustin.gutierrez@amd.com, pavle.kotarac@amd.com Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" From: Iswara Nagulendran [HOW&WHY] EDP link detection must be updated to support a primary EDP with a link index of greater than 0. * SWDEV-342936 - dc: DSC bringup for SAG 1.5 [WHY] SmartAccess Graphics 1.5 (a.k.a SmartMux 1.5) requires seamless switching between GPUs with DSC enabled. [HOW] Moved DSC programming to apply_single_control_ctx_to_hw before the stream enablement logic to ensure the CRC checker provides valid values for non-black frames allowing the system to come out of forced PSR on d2i. Added additional logic to both generate a black frame through setVisibility calls and keep track of the CRCs values for this black frame when coming out of forced PSR. Updating logic for DalRegKey_DisableDSC to disable DSC on EDP and all ports for systems. [CLEANED] dc: Moved DSC programming to before stream enablement [HOW&WHY] Moved DSC programming to apply_single_control_ctx_to_hw before the stream enablement logic. Co-authored-by: sregolui Reviewed-by: Jayendran Ramani Reviewed-by: Harry Vanzylldejong Acked-by: Brian Chang Signed-off-by: sregolui Signed-off-by: Iswara Nagulendran --- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 12 ------------ .../drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 13 +++++++++++++ 2 files changed, 13 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index 74db87f3dc6f..38fa63d43ad9 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -4303,18 +4303,6 @@ void core_link_enable_stream( if (pipe_ctx->stream->dpms_off) return; - /* Have to setup DSC before DIG FE and BE are connected (which happens before the - * link training). This is to make sure the bandwidth sent to DIG BE won't be - * bigger than what the link and/or DIG BE can handle. VBID[6]/CompressedStream_flag - * will be automatically set at a later time when the video is enabled - * (DP_VID_STREAM_EN = 1). - */ - if (pipe_ctx->stream->timing.flags.DSC) { - if (dc_is_dp_signal(pipe_ctx->stream->signal) || - dc_is_virtual_signal(pipe_ctx->stream->signal)) - dp_set_dsc_enable(pipe_ctx, true); - } - status = enable_link(state, pipe_ctx); if (status != DC_OK) { diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 801206aed63a..fe346e96c2d1 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1577,6 +1577,19 @@ static enum dc_status apply_single_controller_ctx_to_hw( if (dc_is_dp_signal(pipe_ctx->stream->signal)) dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_CONNECT_DIG_FE_OTG); + /* Have to setup DSC before DIG FE and BE are connected (which happens before the + * link training). This is to make sure the bandwidth sent to DIG BE won't be + * bigger than what the link and/or DIG BE can handle. VBID[6]/CompressedStream_flag + * will be automatically set at a later time when the video is enabled + * (DP_VID_STREAM_EN = 1). + */ + if (pipe_ctx->stream->timing.flags.DSC) { + if (dc_is_dp_signal(pipe_ctx->stream->signal) || + dc_is_virtual_signal(pipe_ctx->stream->signal)) + dp_set_dsc_enable(pipe_ctx, true); + + } + if (!stream->dpms_off) { if (dc->hwss.update_phy_state) dc->hwss.update_phy_state(context, pipe_ctx, TX_ON_SYMCLK_ON); -- 2.25.1