From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3F70DC4332F for ; Sun, 9 Oct 2022 23:53:11 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9992210E594; Sun, 9 Oct 2022 23:53:06 +0000 (UTC) Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by gabe.freedesktop.org (Postfix) with ESMTPS id 376DF10E58C; Sun, 9 Oct 2022 23:52:59 +0000 (UTC) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id D584AB80DE4; Sun, 9 Oct 2022 23:52:57 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B2FCDC43470; Sun, 9 Oct 2022 23:52:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1665359576; bh=D57F51nhXs+6rwTKvULIB5lh9K58TqPulJrZALO2lFY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=enQFCB6L9MIc5T3r0cwbsHiVtp1Nc0s/EcA5DmsQFPG0VilIxWFr3G4/j1CLF6JjE 0X4eQ1HGMCPHZmNVDv+mNb6vyJeGxVDXfFradgrKG3CU5UctMZsjSeZupLIGv4pyiJ mI8jBKanLb9gU9BnjAJgzKLRsrMu0xHckeb8nGslNDWV/gU3ZUL608KBermg2pvCMC pMJiKHlKCPRKy6LCTBkQm0604xXukF2XuPTR8KD1cWN+mwQcPW6F91tOHmnTIqy2+5 Bsl+MNznd2WKI1ftn1XBJiYgOscyyOPs5ncn2+IrGNRnRVTM7MtZb1pzsd0Bn9eOGn 9Yk1LLNIzZ1uA== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Subject: [PATCH AUTOSEL 5.19 11/36] drm/amdgpu: Skip the program of MMMC_VM_AGP_* in SRIOV on MMHUB v3_0_0 Date: Sun, 9 Oct 2022 19:51:57 -0400 Message-Id: <20221009235222.1230786-11-sashal@kernel.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221009235222.1230786-1-sashal@kernel.org> References: <20221009235222.1230786-1-sashal@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 X-stable: review X-Patchwork-Hint: Ignore Content-Transfer-Encoding: 8bit X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sasha Levin , Jack.Xiao@amd.com, tianci.yin@amd.com, Jack.Gui@amd.com, Horace Chen , Xinhui.Pan@amd.com, aaron.liu@amd.com, amd-gfx@lists.freedesktop.org, ray.huang@amd.com, dri-devel@lists.freedesktop.org, daniel@ffwll.ch, Alex Deucher , Yifan Zha , evan.quan@amd.com, airlied@gmail.com, =?UTF-8?q?Christian=20K=C3=B6nig?= , Hawking Zhang Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" From: Yifan Zha [ Upstream commit c1026c6f319724dc88fc08d9d9d35bcbdf492b42 ] [Why] VF should not program these registers, the value were defined in the host. [How] Skip writing them in SRIOV environment and program them on host side. Acked-by: Christian König Signed-off-by: Yifan Zha Signed-off-by: Horace Chen Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin --- drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c index bc11b2de37ae..a1d26c4d80b8 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c @@ -169,17 +169,17 @@ static void mmhub_v3_0_init_system_aperture_regs(struct amdgpu_device *adev) uint64_t value; uint32_t tmp; - /* Disable AGP. */ - WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE, 0); - WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, 0); - WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, 0x00FFFFFF); - if (!amdgpu_sriov_vf(adev)) { /* * the new L1 policy will block SRIOV guest from writing * these regs, and they will be programed at host. * so skip programing these regs. */ + /* Disable AGP. */ + WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE, 0); + WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, 0); + WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, 0x00FFFFFF); + /* Program the system aperture low logical page number. */ WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR, adev->gmc.vram_start >> 18); -- 2.35.1