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Thu, 13 Oct 2022 03:28:56 -0500 From: Victor Zhao To: Subject: [PATCH 3/3] drm/amdgpu: Refactor mode2 reset logic for v11.0.7 Date: Thu, 13 Oct 2022 16:27:45 +0800 Message-ID: <20221013082745.46143-3-Victor.Zhao@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221013082745.46143-1-Victor.Zhao@amd.com> References: <20221013082745.46143-1-Victor.Zhao@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT084:EE_|CY5PR12MB6456:EE_ X-MS-Office365-Filtering-Correlation-Id: 409aa23f-3003-4575-9d5a-08daacf4fa27 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: xpa8w2n1/iEsvsjnXuf+W5ny+VWXYAXjQqZ8irFXeIc9ReVmLs0uVv2odSGqRQb4b3uTu0PiVAsD+riKnF/Tj772OW37uMf83mp/puhgqEDG6aEK5K3UMTiIk9XJF6SgyZVK2BM59oFQoY2Nucci5CJ6ImO6nVXWI0Fsv4Bn4b21biJWtxsiO21gQ78IwBJXU8tb9fgc/WX5WE/2UZ270RNTjwdyCDMnR+jCjYRpIV8r0LRxgIdz4Mk1GlEKbKkylMbNTO/PwofHRyU2alTrPqOG9Zwi2c7neS0/GqdP8LQUG47Plq3M6s7tcFaQ/nsRd1jh29bXoy4YUTl7TUCmQdpTb5eG2KBx+F73BWpiVlOgWraW74B+J9Rzk+ZQXWq2riuPmCFs5MLImzSJvCChBBfQxrW5OgIogmVnUQYsUZ6aofHWTcm75qGUStxV1dWbvzNuOhUi+IAZVy05LbkHiZasd+KqDASEeWpUWKyPFACRTwUamiDUeH6miDxe4al/lZBvBBl3KnRqJ500J3SCtVSCoiXyDwe/gi9+vZxjpLt1wb3tPLIwB/obSMDCjIwxvNzZr1yVw/xsJA1i2xO545/wA03TM+EeyBn6ZvVjkC28X2w2bdI8aJLbMuiCvSxNULiBP6hj59yGwobHL55NpigThMNkmFTWIxaksp69o8lj4ext3VHTg8A/EbmG64XhZXBAsA17RbzzdCc0vf/6NUfnt6i/TWqoxzq+52RHTm9/WjwUYqon4t984W+zhtS40ypojBzmph2j+JHsMlqw+DrY16sekb+zSkUpHnRegMfO8qvCFEIwO7SWaIovKkDx X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230022)(4636009)(39860400002)(136003)(376002)(396003)(346002)(451199015)(36840700001)(40470700004)(46966006)(54906003)(40460700003)(41300700001)(356005)(2906002)(8936002)(6916009)(81166007)(36860700001)(70206006)(316002)(86362001)(4326008)(82310400005)(8676002)(7696005)(40480700001)(6666004)(2616005)(70586007)(1076003)(5660300002)(478600001)(26005)(83380400001)(426003)(82740400003)(336012)(186003)(36756003)(47076005)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2022 08:28:59.4463 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 409aa23f-3003-4575-9d5a-08daacf4fa27 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT084.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6456 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrey.Grodzovsky@amd.com, Lijo.Lazar@amd.com, Victor Zhao Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" - refactor mode2 on v11.0.7 to align with aldebaran - comment out using mode2 reset as default for now, will introduce another controller to replace previous reset_level_mask Signed-off-by: Victor Zhao --- drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c | 23 ++++++++++++++------- 1 file changed, 16 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c b/drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c index 7aa570c1ce4a..a096f0b740ce 100644 --- a/drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c +++ b/drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c @@ -31,6 +31,17 @@ #include "amdgpu_psp.h" #include "amdgpu_xgmi.h" +static bool sienna_cichlid_is_mode2_default(struct amdgpu_reset_control *reset_ctl) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle; +#if 0 + if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7) && + adev->pm.fw_version >= 0x3a5500 && !amdgpu_sriov_vf(adev)) + return true; +#endif + return false; +} + static struct amdgpu_reset_handler * sienna_cichlid_get_reset_handler(struct amdgpu_reset_control *reset_ctl, struct amdgpu_reset_context *reset_context) @@ -44,15 +55,13 @@ sienna_cichlid_get_reset_handler(struct amdgpu_reset_control *reset_ctl, if (handler->reset_method == reset_context->method) return handler; } - } else { - list_for_each_entry(handler, &reset_ctl->reset_handlers, + } + + if (sienna_cichlid_is_mode2_default(reset_ctl)) { + list_for_each_entry (handler, &reset_ctl->reset_handlers, handler_list) { - if (handler->reset_method == AMD_RESET_METHOD_MODE2 && - adev->pm.fw_version >= 0x3a5500 && - !amdgpu_sriov_vf(adev)) { - reset_context->method = AMD_RESET_METHOD_MODE2; + if (handler->reset_method == AMD_RESET_METHOD_MODE2) return handler; - } } } -- 2.25.1