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From: Sasha Levin <sashal@kernel.org>
To: linux-kernel@vger.kernel.org, stable@vger.kernel.org
Cc: Sasha Levin <sashal@kernel.org>,
	Brian Chang <Brian.Chang@amd.com>,
	Ethan.Wellenreiter@amd.com, Dillon Varone <Dillon.Varone@amd.com>,
	sunpeng.li@amd.com, airlied@gmail.com,
	dri-devel@lists.freedesktop.org, Xinhui.Pan@amd.com,
	Rodrigo.Siqueira@amd.com, Syed.Hassan@amd.com,
	amd-gfx@lists.freedesktop.org,
	Daniel Wheeler <daniel.wheeler@amd.com>,
	Alvin Lee <Alvin.Lee2@amd.com>,
	daniel@ffwll.ch, Martin Leung <Martin.Leung@amd.com>,
	Alex Deucher <alexander.deucher@amd.com>,
	Jun.Lei@amd.com, harry.wentland@amd.com,
	christian.koenig@amd.com
Subject: [PATCH AUTOSEL 6.0 36/39] drm/amd/display: Use viewport height for subvp mall allocation size
Date: Mon, 28 Nov 2022 12:36:16 -0500	[thread overview]
Message-ID: <20221128173642.1441232-36-sashal@kernel.org> (raw)
In-Reply-To: <20221128173642.1441232-1-sashal@kernel.org>

From: Dillon Varone <Dillon.Varone@amd.com>

[ Upstream commit dd2c028c1395d622df7ddd6837f8ab2dc94008ee ]

[WHY?]
MALL allocation size depends on the viewport height, not the addressable
vertical lines, which will not match when scaling.

[HOW?]
Base MALL allocation size calculations off viewport height.

Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com>
Reviewed-by: Martin Leung <Martin.Leung@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Dillon Varone <Dillon.Varone@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
index 13cd1f2e50ca..902c69d126d5 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
@@ -101,7 +101,7 @@ uint32_t dcn32_helper_calculate_num_ways_for_subvp(struct dc *dc, struct dc_stat
 			mall_alloc_width_blk_aligned = full_vp_width_blk_aligned;
 
 			/* mall_alloc_height_blk_aligned_l/c = CEILING(sub_vp_height_l/c - 1, blk_height_l/c) + blk_height_l/c */
-			mall_alloc_height_blk_aligned = (pipe->stream->timing.v_addressable - 1 + mblk_height - 1) /
+			mall_alloc_height_blk_aligned = (pipe->plane_res.scl_data.viewport.height - 1 + mblk_height - 1) /
 					mblk_height * mblk_height + mblk_height;
 
 			/* full_mblk_width_ub_l/c = mall_alloc_width_blk_aligned_l/c;
-- 
2.35.1


       reply	other threads:[~2022-11-28 17:39 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <20221128173642.1441232-1-sashal@kernel.org>
2022-11-28 17:36 ` Sasha Levin [this message]
2022-11-28 17:36 ` [PATCH AUTOSEL 6.0 37/39] drm/amd/display: Avoid setting pixel rate divider to N/A Sasha Levin
2022-11-28 17:36 ` [PATCH AUTOSEL 6.0 38/39] drm/amd/display: Use new num clk levels struct for max mclk index Sasha Levin
2022-11-28 17:36 ` [PATCH AUTOSEL 6.0 39/39] drm/amdgpu: fix use-after-free during gpu recovery Sasha Levin

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