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DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Feb 2023 19:09:34.7092 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 955cbfc9-c426-4d4e-6ed8-08db061a300b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000B8E8.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB6781 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alexander.deucher@amd.com, christian.koenig@amd.com, shashank.sharma@amd.com Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" From: Alex Deucher This patch initializes doorbell pool with bar manager, which will divide all the doorbell memory into pages. Signed-off-by: Alex Deucher Signed-off-by: Shashank Sharma --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index e04409210415..95017de6b23d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -1837,6 +1837,13 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) if (r) return r; + /* Initialize DOORBELL pool with all of DOORBELL divided into pages */ + r = amdgpu_bar_mgr_init(adev, AMDGPU_PL_DOORBELL); + if (r) { + DRM_ERROR("Failed initializing DOORBELL heap.\n"); + return r; + } + /* *The reserved vram for firmware must be pinned to the specified *place on the VRAM, so reserve it early. @@ -1890,6 +1897,9 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) DRM_INFO("amdgpu: %uM of VRAM memory ready\n", (unsigned) (adev->gmc.real_vram_size / (1024 * 1024))); + DRM_INFO("amdgpu: %uM of DOORBELL memory ready\n", + (unsigned) (adev->gmc.doorbell_aper_size / (1024 * 1024))); + /* Compute GTT size, either based on 1/2 the size of RAM size * or whatever the user passed on module init */ if (amdgpu_gtt_size == -1) { @@ -1991,6 +2001,7 @@ void amdgpu_ttm_fini(struct amdgpu_device *adev) } amdgpu_bar_mgr_fini(adev, TTM_PL_VRAM); + amdgpu_bar_mgr_fini(adev, AMDGPU_PL_DOORBELL); amdgpu_gtt_mgr_fini(adev); amdgpu_preempt_mgr_fini(adev); ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GDS); -- 2.34.1