From: Sasha Levin <sashal@kernel.org>
To: linux-kernel@vger.kernel.org, stable@vger.kernel.org
Cc: Sasha Levin <sashal@kernel.org>,
stylon.wang@amd.com, amd-gfx@lists.freedesktop.org,
aurabindo.pillai@amd.com, sunpeng.li@amd.com, airlied@gmail.com,
dri-devel@lists.freedesktop.org, Xinhui.Pan@amd.com,
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>,
steve.su@amd.com, HaoPing.Liu@amd.com, alex.hung@amd.com,
Daniel Wheeler <Daniel.Wheeler@amd.com>,
Brandon Syu <Brandon.Syu@amd.com>,
Alvin.Lee2@amd.com, daniel@ffwll.ch,
Martin Leung <Martin.Leung@amd.com>,
Alex Deucher <alexander.deucher@amd.com>,
Paul.Hsieh@amd.com, harry.wentland@amd.com,
christian.koenig@amd.com
Subject: [PATCH AUTOSEL 6.2 17/60] drm/amd/display: fix mapping to non-allocated address
Date: Sun, 26 Feb 2023 21:00:02 -0500 [thread overview]
Message-ID: <20230227020045.1045105-17-sashal@kernel.org> (raw)
In-Reply-To: <20230227020045.1045105-1-sashal@kernel.org>
From: Brandon Syu <Brandon.Syu@amd.com>
[ Upstream commit 9190d4a263264eabf715f5fc1827da45e3fdc247 ]
[Why]
There is an issue mapping non-allocated location of memory.
It would allocate gpio registers from an array out of bounds.
[How]
Patch correct numbers of bounds for using.
Tested-by: Daniel Wheeler <Daniel.Wheeler@amd.com>
Reviewed-by: Martin Leung <Martin.Leung@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Brandon Syu <Brandon.Syu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
.../gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c | 6 ++++--
.../gpu/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.c | 6 ++++--
.../gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c | 6 ++++--
drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h | 7 +++++++
4 files changed, 19 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c
index 9b63c6c0cc844..e0bd0c722e006 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c
@@ -138,7 +138,8 @@ static const struct ddc_sh_mask ddc_shift[] = {
DDC_MASK_SH_LIST_DCN2(__SHIFT, 3),
DDC_MASK_SH_LIST_DCN2(__SHIFT, 4),
DDC_MASK_SH_LIST_DCN2(__SHIFT, 5),
- DDC_MASK_SH_LIST_DCN2(__SHIFT, 6)
+ DDC_MASK_SH_LIST_DCN2(__SHIFT, 6),
+ DDC_MASK_SH_LIST_DCN2_VGA(__SHIFT)
};
static const struct ddc_sh_mask ddc_mask[] = {
@@ -147,7 +148,8 @@ static const struct ddc_sh_mask ddc_mask[] = {
DDC_MASK_SH_LIST_DCN2(_MASK, 3),
DDC_MASK_SH_LIST_DCN2(_MASK, 4),
DDC_MASK_SH_LIST_DCN2(_MASK, 5),
- DDC_MASK_SH_LIST_DCN2(_MASK, 6)
+ DDC_MASK_SH_LIST_DCN2(_MASK, 6),
+ DDC_MASK_SH_LIST_DCN2_VGA(_MASK)
};
#include "../generic_regs.h"
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.c
index 687d4f128480e..36a5736c58c92 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.c
@@ -145,7 +145,8 @@ static const struct ddc_sh_mask ddc_shift[] = {
DDC_MASK_SH_LIST_DCN2(__SHIFT, 3),
DDC_MASK_SH_LIST_DCN2(__SHIFT, 4),
DDC_MASK_SH_LIST_DCN2(__SHIFT, 5),
- DDC_MASK_SH_LIST_DCN2(__SHIFT, 6)
+ DDC_MASK_SH_LIST_DCN2(__SHIFT, 6),
+ DDC_MASK_SH_LIST_DCN2_VGA(__SHIFT)
};
static const struct ddc_sh_mask ddc_mask[] = {
@@ -154,7 +155,8 @@ static const struct ddc_sh_mask ddc_mask[] = {
DDC_MASK_SH_LIST_DCN2(_MASK, 3),
DDC_MASK_SH_LIST_DCN2(_MASK, 4),
DDC_MASK_SH_LIST_DCN2(_MASK, 5),
- DDC_MASK_SH_LIST_DCN2(_MASK, 6)
+ DDC_MASK_SH_LIST_DCN2(_MASK, 6),
+ DDC_MASK_SH_LIST_DCN2_VGA(_MASK)
};
#include "../generic_regs.h"
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c
index 9fd8b269dd79c..985f10b397509 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c
@@ -149,7 +149,8 @@ static const struct ddc_sh_mask ddc_shift[] = {
DDC_MASK_SH_LIST_DCN2(__SHIFT, 3),
DDC_MASK_SH_LIST_DCN2(__SHIFT, 4),
DDC_MASK_SH_LIST_DCN2(__SHIFT, 5),
- DDC_MASK_SH_LIST_DCN2(__SHIFT, 6)
+ DDC_MASK_SH_LIST_DCN2(__SHIFT, 6),
+ DDC_MASK_SH_LIST_DCN2_VGA(__SHIFT)
};
static const struct ddc_sh_mask ddc_mask[] = {
@@ -158,7 +159,8 @@ static const struct ddc_sh_mask ddc_mask[] = {
DDC_MASK_SH_LIST_DCN2(_MASK, 3),
DDC_MASK_SH_LIST_DCN2(_MASK, 4),
DDC_MASK_SH_LIST_DCN2(_MASK, 5),
- DDC_MASK_SH_LIST_DCN2(_MASK, 6)
+ DDC_MASK_SH_LIST_DCN2(_MASK, 6),
+ DDC_MASK_SH_LIST_DCN2_VGA(_MASK)
};
#include "../generic_regs.h"
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h b/drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h
index 308a543178a56..59884ef651b39 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h
+++ b/drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h
@@ -113,6 +113,13 @@
(PHY_AUX_CNTL__AUX## cd ##_PAD_RXSEL## mask_sh),\
(DC_GPIO_AUX_CTRL_5__DDC_PAD## cd ##_I2CMODE## mask_sh)}
+#define DDC_MASK_SH_LIST_DCN2_VGA(mask_sh) \
+ {DDC_MASK_SH_LIST_COMMON(mask_sh),\
+ 0,\
+ 0,\
+ 0,\
+ 0}
+
struct ddc_registers {
struct gpio_registers gpio;
uint32_t ddc_setup;
--
2.39.0
next prev parent reply other threads:[~2023-02-27 2:02 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20230227020045.1045105-1-sashal@kernel.org>
2023-02-27 1:59 ` [PATCH AUTOSEL 6.2 03/60] drm/amd/display: Reduce expected sdp bandwidth for dcn321 Sasha Levin
2023-02-27 1:59 ` [PATCH AUTOSEL 6.2 04/60] drm/amd/display: Revert Reduce delay when sink device not able to ACK 00340h write Sasha Levin
2023-02-27 1:59 ` [PATCH AUTOSEL 6.2 05/60] drm/amd/display: Fix potential null-deref in dm_resume Sasha Levin
2023-02-27 1:59 ` [PATCH AUTOSEL 6.2 09/60] drm/amd/display: Defer DIG FIFO disable after VID stream enable Sasha Levin
2023-02-27 1:59 ` [PATCH AUTOSEL 6.2 10/60] drm/radeon: free iio for atombios when driver shutdown Sasha Levin
2023-02-27 1:59 ` [PATCH AUTOSEL 6.2 11/60] drm/amd: Avoid BUG() for case of SRIOV missing IP version Sasha Levin
2023-02-27 1:59 ` [PATCH AUTOSEL 6.2 12/60] drm/amdkfd: Page aligned memory reserve size Sasha Levin
2023-02-27 2:00 ` [PATCH AUTOSEL 6.2 15/60] drm/amd: Avoid ASSERT for some message failures Sasha Levin
2023-02-27 2:00 ` [PATCH AUTOSEL 6.2 16/60] drm: amd: display: Fix memory leakage Sasha Levin
2023-02-27 2:00 ` Sasha Levin [this message]
2023-02-27 2:00 ` [PATCH AUTOSEL 6.2 28/60] drm/amd/display: Set hvm_enabled flag for S/G mode Sasha Levin
2023-02-27 2:00 ` [PATCH AUTOSEL 6.2 38/60] Revert "drm/amdgpu: TA unload messages are not actually sent to psp when amdgpu is uninstalled" Sasha Levin
2023-02-27 2:00 ` [PATCH AUTOSEL 6.2 39/60] drm/amd/display: fix FCLK pstate change underflow Sasha Levin
2023-02-27 2:00 ` [PATCH AUTOSEL 6.2 45/60] drm/amd/display: Do not set DRR on pipe commit Sasha Levin
2023-02-27 2:00 ` [PATCH AUTOSEL 6.2 46/60] drm/amd/display: Do not commit pipe when updating DRR Sasha Levin
2023-02-27 2:00 ` [PATCH AUTOSEL 6.2 50/60] drm/amd/display: Move DCN314 DOMAIN power control to DMCUB Sasha Levin
2023-02-27 2:00 ` [PATCH AUTOSEL 6.2 51/60] drm/amd/display: Enable P-state validation checks for DCN314 Sasha Levin
2023-02-27 2:00 ` [PATCH AUTOSEL 6.2 53/60] drm/amd/display: Disable HUBP/DPP PG on DCN314 for now Sasha Levin
2023-02-27 2:00 ` [PATCH AUTOSEL 6.2 54/60] drm/amd/display: disable SubVP + DRR to prevent underflow Sasha Levin
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