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CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230028)(4636009)(346002)(376002)(396003)(39860400002)(136003)(451199021)(46966006)(40470700004)(36840700001)(82740400003)(44832011)(7696005)(70586007)(6916009)(70206006)(2906002)(6666004)(1076003)(8936002)(40480700001)(336012)(426003)(186003)(16526019)(83380400001)(8676002)(2616005)(26005)(41300700001)(36860700001)(5660300002)(40460700003)(316002)(47076005)(86362001)(54906003)(36756003)(4326008)(81166007)(356005)(82310400005)(478600001)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Apr 2023 17:39:19.6502 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 075a5f51-d340-4f4e-2b62-08db44ead57e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT052.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5125 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pierre-eric.pelloux-prayer@amd.com, Shashank Sharma , arvind.yadav@amd.com, Alex Deucher , contactshashanksharma@gmail.com, Christian Koenig Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" To support oversubscription, MES FW expects WPTR BOs to be mapped into GART, before they are submitted to usermode queues. This patch adds a function for the same. V4: fix the wptr value before mapping lookup (Bas, Christian). Cc: Alex Deucher Cc: Christian Koenig Signed-off-by: Arvind Yadav Signed-off-by: Shashank Sharma --- drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c | 90 +++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 1 + .../gpu/drm/amd/include/amdgpu_userqueue.h | 1 + 3 files changed, 92 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c index e95fb35b0cb5..385cd51b6c96 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c @@ -44,6 +44,89 @@ amdgpu_userqueue_find(struct amdgpu_userq_mgr *uq_mgr, int qid) return idr_find(&uq_mgr->userq_idr, qid); } +static int +amdgpu_userqueue_map_gtt_bo_to_gart(struct amdgpu_device *adev, struct amdgpu_bo *bo) +{ + int ret; + + ret = amdgpu_bo_reserve(bo, true); + if (ret) { + DRM_ERROR("Failed to reserve bo. ret %d\n", ret); + goto err_reserve_bo_failed; + } + + ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT); + if (ret) { + DRM_ERROR("Failed to pin bo. ret %d\n", ret); + goto err_pin_bo_failed; + } + + ret = amdgpu_ttm_alloc_gart(&bo->tbo); + if (ret) { + DRM_ERROR("Failed to bind bo to GART. ret %d\n", ret); + goto err_map_bo_gart_failed; + } + + amdgpu_bo_unreserve(bo); + bo = amdgpu_bo_ref(bo); + + return 0; + +err_map_bo_gart_failed: + amdgpu_bo_unpin(bo); +err_pin_bo_failed: + amdgpu_bo_unreserve(bo); +err_reserve_bo_failed: + + return ret; +} + + +static int +amdgpu_userqueue_create_wptr_mapping(struct amdgpu_device *adev, + struct drm_file *filp, + struct amdgpu_usermode_queue *queue) +{ + struct amdgpu_bo_va_mapping *wptr_mapping; + struct amdgpu_vm *wptr_vm; + struct amdgpu_bo *wptr_bo = NULL; + uint64_t wptr = queue->userq_prop.wptr_gpu_addr; + int ret; + + wptr_vm = queue->vm; + ret = amdgpu_bo_reserve(wptr_vm->root.bo, false); + if (ret) + goto err_wptr_map_gart; + + wptr &= AMDGPU_GMC_HOLE_MASK; + wptr_mapping = amdgpu_vm_bo_lookup_mapping(wptr_vm, wptr >> PAGE_SHIFT); + amdgpu_bo_unreserve(wptr_vm->root.bo); + if (!wptr_mapping) { + DRM_ERROR("Failed to lookup wptr bo\n"); + ret = -EINVAL; + goto err_wptr_map_gart; + } + + wptr_bo = wptr_mapping->bo_va->base.bo; + if (wptr_bo->tbo.base.size > PAGE_SIZE) { + DRM_ERROR("Requested GART mapping for wptr bo larger than one page\n"); + ret = -EINVAL; + goto err_wptr_map_gart; + } + + ret = amdgpu_userqueue_map_gtt_bo_to_gart(adev, wptr_bo); + if (ret) { + DRM_ERROR("Failed to map wptr bo to GART\n"); + goto err_wptr_map_gart; + } + + queue->wptr_mc_addr = wptr_bo->tbo.resource->start << PAGE_SHIFT; + return 0; + +err_wptr_map_gart: + return ret; +} + static int amdgpu_userqueue_create_gfx(struct drm_file *filp, union drm_amdgpu_userq *args) { struct amdgpu_usermode_queue *queue; @@ -81,6 +164,13 @@ static int amdgpu_userqueue_create_gfx(struct drm_file *filp, union drm_amdgpu_u goto free_queue; } + r = amdgpu_userqueue_create_wptr_mapping(uq_mgr->adev, filp, queue); + if (r) { + DRM_ERROR("Failed to map WPTR (0x%llx) for userqueue\n", + queue->userq_prop.wptr_gpu_addr); + goto free_queue; + } + if (uq_mgr->userq_funcs[queue->queue_type]->mqd_create) { r = uq_mgr->userq_funcs[queue->queue_type]->mqd_create(uq_mgr, queue); if (r) { diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index 7a45d68091ec..6eeae0206d8a 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -6439,6 +6439,7 @@ static int gfx_v11_userq_map(struct amdgpu_userq_mgr *uq_mgr, queue_input.queue_size = queue->userq_prop.queue_size >> 2; queue_input.doorbell_offset = queue->userq_prop.doorbell_index; queue_input.page_table_base_addr = amdgpu_gmc_pd_addr(queue->vm->root.bo); + queue_input.wptr_mc_addr = queue->wptr_mc_addr; amdgpu_mes_lock(&adev->mes); r = adev->mes.funcs->add_hw_queue(&adev->mes, &queue_input); diff --git a/drivers/gpu/drm/amd/include/amdgpu_userqueue.h b/drivers/gpu/drm/amd/include/amdgpu_userqueue.h index 11e8ad649f6e..0001ecd710a7 100644 --- a/drivers/gpu/drm/amd/include/amdgpu_userqueue.h +++ b/drivers/gpu/drm/amd/include/amdgpu_userqueue.h @@ -38,6 +38,7 @@ struct amdgpu_usermode_queue { int queue_id; int queue_type; uint64_t doorbell_handle; + uint64_t wptr_mc_addr; uint64_t proc_ctx_gpu_addr; uint64_t gang_ctx_gpu_addr; uint64_t gds_ctx_gpu_addr; -- 2.40.0