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Wed, 16 Aug 2023 01:07:01 -0500 From: Wayne Lin To: Subject: [PATCH 00/16] DC Patches August 18, 2023 Date: Wed, 16 Aug 2023 14:06:42 +0800 Message-ID: <20230816060658.2141009-1-Wayne.Lin@amd.com> X-Mailer: git-send-email 2.37.3 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000971E6:EE_|PH8PR12MB7349:EE_ X-MS-Office365-Filtering-Correlation-Id: 81483a43-2f6d-4d57-4c25-08db9e1f084f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: GlhO4AfjZgK7fq+8MEtBiJUrJNRVqQLailQf8lV0kJ+EKxj3OXgggjCFOBc0E/hMJlgDVRRMA5nrtL8k92V5xRuQhrWAcl+LWJWZgIYGydazMkh+F7gVhTJ8rhWeduyqImy20Z/qalj7iCpCbg+iS6AL06nEhmV08g6eJDXzzDfTFwTrGerYZJLIOk8GGIROFAUZQdGRcwWQHl1Koc9sCrJTAzBL9dqg8ziEVqIH1eDZa3xAFBODhABaM+PVM7D9gUrOk0CZyL8zsIu1Z8HWrhXc8AG6NNdN4BuXB4KrAqb6YbGkrFoH5JfOU7vnAuAO+EgDxbkHZWYff4wdy5JId0eBhr8/pWwhsr6FgYRKj4KhBhSTj+sUGAL6wgaToHbw/zQEprcnD3SwqXWb5VHJJM5q6NZPFOa5NiPiVeJiNegzjOk/u00bGew7lsGBHWo/A0xDRjGKttsxzhPmgYfzxTSgEg1jcS1qs5+5xIfldnXhm/0PBo9IGI5aQti69+LxYOCnQmkevwUoYguEMqvYs+Vis/kcmJzGGbqup97zTwXsNfB2/ekq4oni+JFtCgpI+vgYq5CPPvtw1nJYWa2EPoH8+9HNodB+zM7ZaUQQRT6Pdz4BQWSnBQ3ciIQbBTxVqGXLFNAk5qmY668Wfr765ag/HQNdoGXbmW30/iuxGB+tjScGbmXuWcD3faZKvSMeIgRgiLzUyA2Q69suIY/AZq1xp3mnjL3UHlSn0kCPwEoM2i5xeww9uzTZ2+61LlVV4DJqUa6xz6ek2gu4Llc6Sg== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230031)(4636009)(376002)(39860400002)(396003)(346002)(136003)(1800799009)(82310400011)(451199024)(186009)(46966006)(36840700001)(40470700004)(6666004)(54906003)(70586007)(70206006)(7696005)(2906002)(478600001)(1076003)(336012)(426003)(26005)(6916009)(5660300002)(2616005)(83380400001)(41300700001)(316002)(47076005)(36860700001)(8936002)(4326008)(82740400003)(8676002)(81166007)(356005)(40460700003)(36756003)(86362001)(40480700001)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Aug 2023 06:07:12.2084 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 81483a43-2f6d-4d57-4c25-08db9e1f084f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000971E6.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB7349 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: stylon.wang@amd.com, Sunpeng.Li@amd.com, Harry.Wentland@amd.com, qingqing.zhuo@amd.com, Rodrigo.Siqueira@amd.com, roman.li@amd.com, solomon.chiu@amd.com, Daniel Wheeler , Aurabindo.Pillai@amd.com, Wayne Lin , Bhawanpreet.Lakha@amd.com, agustin.gutierrez@amd.com, pavle.kotarac@amd.com Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" This DC patchset brings improvements in multiple areas. In summary, we have: - Ensure FS is enabled before sending request to DMUB for FS changes - Add check for PMFW hard min request complete - Save addr update in scratch before flip - Fix static screen detection setting - Write flip addr to scratch reg for subvp - set minimum of VBlank_nom - Correct unit conversion for vstartup - Roll back unit correction - Enable runtime register offset init for DCN32 DMUB - Refactor edp power control - PQ regamma end point - PQ tail accuracy - Blank phantom OTG before enabling - Expose mall capability Cc: Daniel Wheeler --- Alvin Lee (3): drm/amd/display: Blank phantom OTG before enabling drm/amd/display: Write flip addr to scratch reg for subvp drm/amd/display: Save addr update in scratch before flip Anthony Koo (1): drm/amd/display: [FW Promotion] Release 0.0.180.0 Aric Cyr (1): drm/amd/display: 3.2.248 Aurabindo Pillai (2): drm/amd/display: Expose mall capability drm/amd/display: Enable runtime register offset init for DCN32 DMUB ChunTao Tso (1): drm/amd/display: set minimum of VBlank_nom Ian Chen (1): drm/amd/display: Refactor edp power control Krunoslav Kovac (2): drm/amd/display: PQ tail accuracy drm/amd/display: PQ regamma end point Ovidiu Bunea (1): drm/amd/display: Roll back unit correction Reza Amini (1): drm/amd/display: Correct unit conversion for vstartup Samson Tam (2): drm/amd/display: add check for PMFW hard min request complete drm/amd/display: ensure FS is enabled before sending request to DMUB for FS changes SungHuai Wang (1): drm/amd/display: fix static screen detection setting .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 + .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 19 +++ .../drm/amd/display/dc/clk_mgr/dcn32/dalsmc.h | 11 +- .../dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c | 154 +++++++++++++++++- drivers/gpu/drm/amd/display/dc/core/dc.c | 71 +++----- .../drm/amd/display/dc/core/dc_hw_sequencer.c | 23 +++ drivers/gpu/drm/amd/display/dc/dc.h | 6 +- drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 11 +- drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h | 1 + drivers/gpu/drm/amd/display/dc/dc_stream.h | 1 - .../display/dc/dce110/dce110_hw_sequencer.c | 2 +- .../drm/amd/display/dc/dcn20/dcn20_hwseq.c | 22 ++- .../amd/display/dc/dcn30/dcn30_cm_common.c | 104 ++++-------- .../drm/amd/display/dc/dcn30/dcn30_hwseq.c | 17 ++ .../drm/amd/display/dc/dcn30/dcn30_hwseq.h | 2 + .../gpu/drm/amd/display/dc/dcn30/dcn30_init.c | 2 +- .../gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c | 17 -- .../gpu/drm/amd/display/dc/dcn31/dcn31_init.c | 2 +- .../drm/amd/display/dc/dcn314/dcn314_hwseq.c | 3 +- .../drm/amd/display/dc/dcn314/dcn314_init.c | 2 +- .../drm/amd/display/dc/dcn32/dcn32_hwseq.c | 46 ++++++ .../drm/amd/display/dc/dcn32/dcn32_hwseq.h | 5 + .../gpu/drm/amd/display/dc/dcn32/dcn32_init.c | 3 +- .../amd/display/dc/dml/dcn314/dcn314_fpu.c | 21 ++- .../drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 18 ++ .../gpu/drm/amd/display/dc/inc/core_types.h | 2 + .../gpu/drm/amd/display/dc/inc/hw_sequencer.h | 15 +- drivers/gpu/drm/amd/display/dc/inc/link.h | 1 + .../gpu/drm/amd/display/dc/link/link_dpms.c | 9 +- .../drm/amd/display/dc/link/link_factory.c | 1 + .../display/dc/link/protocols/link_dp_phy.c | 3 +- .../link/protocols/link_edp_panel_control.c | 29 ++++ .../link/protocols/link_edp_panel_control.h | 1 + drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 21 ++- .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 5 - .../gpu/drm/amd/display/dmub/src/dmub_dcn32.c | 64 ++++++-- .../gpu/drm/amd/display/dmub/src/dmub_dcn32.h | 17 +- .../gpu/drm/amd/display/dmub/src/dmub_srv.c | 13 ++ .../amd/display/modules/color/color_gamma.c | 115 ++++++++++++- 39 files changed, 674 insertions(+), 190 deletions(-) -- 2.37.3