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Wed, 16 Aug 2023 01:08:10 -0500 From: Wayne Lin To: Subject: [PATCH 07/16] drm/amd/display: Roll back unit correction Date: Wed, 16 Aug 2023 14:06:49 +0800 Message-ID: <20230816060658.2141009-8-Wayne.Lin@amd.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20230816060658.2141009-1-Wayne.Lin@amd.com> References: <20230816060658.2141009-1-Wayne.Lin@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000971E8:EE_|SJ0PR12MB7474:EE_ X-MS-Office365-Filtering-Correlation-Id: addb130c-0a33-4a0d-42f8-08db9e1f2ea1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 9QGxiOyqIlkeO++B1qTB4vW3JkmmGpErPOQDjp9r39zuYlkzBlY9/4PqWRwMJ52wjmARIXpGOCGJeNejgiHOzwZVbgVauAalxzc9t+Y6BKKq/kf1aHv/on6bpMbsW78B1WtrEVJ1Bh8kDX2ApU68LSz4/Ln+Typxcmyruls1B3FQfwADNxB6AY1J7ZGopphpYPkGPkLm0G71pURCIMK7P5N2AOZwGRXJpHLpuq8f6GWBzmkJPJ1HDXn/7srlgBPCxHsnsID6XNTjopSvFwHF/h+bUTZO03szioe27au5QByLWPd803PEkLf8IDq2fcwi+XNi5m3fzAkYsWlszKcMH++xJv7tBYVFGISjC8otaWBV55v1Otrr7QtgoGlLQi85eiCj7wPGKGrbUWm1M1Q4aX/6RDAMDg7kD7w3EY1aKl9ugviVaOe7sVXuJqTFxabePgCOgfLr0p2LyW4zm/F2U5vH1BhXKQsAznMoNNGRbaN+a8MqaEovDNsYiFgWXQF7kVWx6zGfGlwWOcJJoY5xKOMyUL4K7iZi0QUMoG+Js1Dke8PyOVhtE3L4wpmeVpSDXjAU9FWEdwabBHnsWz8R6ubWv9e/tHQzASoSlANB2NNG2+8ftHPOLYsZxKnYQDFBOTjhrsym6awes9Dw7YL5rytZJ8OOkDOmnuXMmYPZDW9ffm5PtbxIRRJYjSOzc02X9BELYo7NKsmEzkvaOqwv+mI0lqGiB1zEkoFQuAd5alb6xq50SMWik/s2fJymtBI48p4qQh28TBvoYwnX5tUSkA== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230031)(4636009)(376002)(39860400002)(396003)(346002)(136003)(1800799009)(82310400011)(451199024)(186009)(46966006)(36840700001)(40470700004)(6666004)(54906003)(70586007)(70206006)(7696005)(2906002)(478600001)(1076003)(336012)(426003)(26005)(6916009)(5660300002)(2616005)(83380400001)(41300700001)(316002)(47076005)(36860700001)(8936002)(4326008)(82740400003)(8676002)(81166007)(356005)(40460700003)(36756003)(86362001)(40480700001)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Aug 2023 06:08:16.4833 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: addb130c-0a33-4a0d-42f8-08db9e1f2ea1 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000971E8.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB7474 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: stylon.wang@amd.com, Reza Amini , Sunpeng.Li@amd.com, Harry.Wentland@amd.com, qingqing.zhuo@amd.com, Rodrigo.Siqueira@amd.com, roman.li@amd.com, solomon.chiu@amd.com, Aurabindo.Pillai@amd.com, Ovidiu Bunea , wayne.lin@amd.com, Bhawanpreet.Lakha@amd.com, agustin.gutierrez@amd.com, pavle.kotarac@amd.com Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" From: Ovidiu Bunea [why] This Unit correction exposes a Replay corruption. [how] This reverts commit: commit 7d3cedf18068 ("drm/amd/display: Correct unit conversion for vstartup") Roll back unit conversion until Replay can fix their corruption. Fixes: 7d3cedf18068 ("drm/amd/display: Correct unit conversion for vstartup") Reviewed-by: Reza Amini Acked-by: Wayne Lin Signed-off-by: Ovidiu Bunea --- .../amd/display/dc/dml/dcn314/dcn314_fpu.c | 25 +------------------ 1 file changed, 1 insertion(+), 24 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c index 07adb614366e..ed8ddb75b333 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c @@ -31,7 +31,6 @@ #include "dml/dcn20/dcn20_fpu.h" #include "dml/dcn31/dcn31_fpu.h" #include "dml/display_mode_vba.h" -#include "dml/dml_inline_defs.h" struct _vcs_dpi_ip_params_st dcn3_14_ip = { .VBlankNomDefaultUS = 668, @@ -274,25 +273,6 @@ static bool is_dual_plane(enum surface_pixel_format format) return format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA; } -/* - * micro_sec_to_vert_lines () - converts time to number of vertical lines for a given timing - * - * @param: num_us: number of microseconds - * @return: number of vertical lines. If exact number of vertical lines is not found then - * it will round up to next number of lines to guarantee num_us - */ -static unsigned int micro_sec_to_vert_lines(unsigned int num_us, struct dc_crtc_timing *timing) -{ - unsigned int num_lines = 0; - unsigned int lines_time_in_ns = 1000.0 * - (((float)timing->h_total * 1000.0) / - ((float)timing->pix_clk_100hz / 10.0)); - - num_lines = dml_ceil(1000.0 * num_us / lines_time_in_ns, 1.0); - - return num_lines; -} - int dcn314_populate_dml_pipes_from_context_fpu(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, bool fast_validate) @@ -309,22 +289,19 @@ int dcn314_populate_dml_pipes_from_context_fpu(struct dc *dc, struct dc_state *c for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { struct dc_crtc_timing *timing; - unsigned int num_lines = 0; if (!res_ctx->pipe_ctx[i].stream) continue; pipe = &res_ctx->pipe_ctx[i]; timing = &pipe->stream->timing; - num_lines = micro_sec_to_vert_lines(dcn3_14_ip.VBlankNomDefaultUS, timing); - if (pipe->stream->adjust.v_total_min != 0) pipes[pipe_cnt].pipe.dest.vtotal = pipe->stream->adjust.v_total_min; else pipes[pipe_cnt].pipe.dest.vtotal = timing->v_total; pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total - pipes[pipe_cnt].pipe.dest.vactive; - pipes[pipe_cnt].pipe.dest.vblank_nom = min(pipes[pipe_cnt].pipe.dest.vblank_nom, num_lines); + pipes[pipe_cnt].pipe.dest.vblank_nom = min(pipes[pipe_cnt].pipe.dest.vblank_nom, dcn3_14_ip.VBlankNomDefaultUS); pipes[pipe_cnt].pipe.dest.vblank_nom = max(pipes[pipe_cnt].pipe.dest.vblank_nom, timing->v_sync_width); pipes[pipe_cnt].pipe.dest.vblank_nom = min(pipes[pipe_cnt].pipe.dest.vblank_nom, max_allowed_vblank_nom); -- 2.37.3