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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SN1PEPF000252A0.mail.protection.outlook.com (10.167.242.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6792.11 via Frontend Transport; Fri, 8 Sep 2023 16:05:03 +0000 Received: from MUN-L-SHSHARMA.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Fri, 8 Sep 2023 11:05:02 -0500 From: Shashank Sharma To: Subject: [PATCH v6 0/9] AMDGPU usermode queues Date: Fri, 8 Sep 2023 18:04:37 +0200 Message-ID: <20230908160446.2188-1-shashank.sharma@amd.com> X-Mailer: git-send-email 2.38.0.windows.1 MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000252A0:EE_|IA1PR12MB8285:EE_ X-MS-Office365-Filtering-Correlation-Id: 75af9011-1a80-4748-58b8-08dbb0855cc8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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SFS:(13230031)(4636009)(376002)(39860400002)(396003)(136003)(346002)(451199024)(186009)(82310400011)(1800799009)(40470700004)(36840700001)(46966006)(40460700003)(966005)(478600001)(6666004)(7696005)(70586007)(70206006)(36860700001)(47076005)(82740400003)(81166007)(356005)(2906002)(41300700001)(40480700001)(83380400001)(336012)(1076003)(26005)(426003)(6916009)(2616005)(86362001)(36756003)(16526019)(44832011)(54906003)(8936002)(4326008)(5660300002)(316002)(8676002)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Sep 2023 16:05:03.6048 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 75af9011-1a80-4748-58b8-08dbb0855cc8 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000252A0.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB8285 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arvind.yadav@amd.com, Shashank Sharma Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" This patch series introduces AMDGPU usermode queues for gfx workloads. Usermode queues is a method of GPU workload submission into the graphics hardware without any interaction with kernel/DRM schedulers. In this method, a userspace graphics application can create its own workqueue and submit it directly in the GPU HW. The general idea of how this is supposed to work: - The application creates the following GPU objetcs: - A queue object to hold the workload packets. - A read pointer object. - A write pointer object. - A doorbell page. - Shadow bufffer pages. - GDS buffer pages (if required). - The application picks a 32-bit offset in the doorbell page for this queue. - The application uses the usermode_queue_create IOCTL introduced in this patch, by passing the GPU addresses of these objects (read ptr, write ptr, queue base address, shadow, gds) with doorbell object and 32-bit doorbell offset in the doorbell page. - The kernel creates the queue and maps it in the HW. - The application can start submitting the data in the queue as soon as the kernel IOCTL returns. - After filling the workload data in the queue, the app must write the number of dwords added in the queue into the doorbell offset, and the GPU will start fetching the data. libDRM changes for this series and a sample DRM test program can be found in the MESA merge request here: https://gitlab.freedesktop.org/mesa/drm/-/merge_requests/287 This patch series depends on the doorbell-manager changes, which were published here (targeted merged in V6.6): https://patchwork.freedesktop.org/series/115802 Alex Deucher (1): drm/amdgpu: UAPI for user queue management Shashank Sharma (8): drm/amdgpu: add usermode queue base code drm/amdgpu: add new IOCTL for usermode queue drm/amdgpu: create GFX-gen11 usermode queue drm/amdgpu: create context space for usermode queue drm/amdgpu: map usermode queue into MES drm/amdgpu: map wptr BO into GART drm/amdgpu: generate doorbell index for userqueue drm/amdgpu: cleanup leftover queues drivers/gpu/drm/amd/amdgpu/Makefile | 2 + drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 + drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 + drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 6 + drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c | 227 ++++++++++++++ drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 292 ++++++++++++++++++ .../gpu/drm/amd/include/amdgpu_userqueue.h | 74 +++++ include/uapi/drm/amdgpu_drm.h | 110 +++++++ 8 files changed, 715 insertions(+) create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c create mode 100644 drivers/gpu/drm/amd/include/amdgpu_userqueue.h -- 2.42.0