From: Sasha Levin <sashal@kernel.org>
To: linux-kernel@vger.kernel.org, stable@vger.kernel.org
Cc: Sasha Levin <sashal@kernel.org>,
Dillon Varone <dillon.varone@amd.com>,
chris.park@amd.com, Alex Hung <alex.hung@amd.com>,
airlied@gmail.com, dri-devel@lists.freedesktop.org,
Xinhui.Pan@amd.com, Rodrigo.Siqueira@amd.com,
amd-gfx@lists.freedesktop.org, nathan@kernel.org,
sunpeng.li@amd.com, Daniel Wheeler <daniel.wheeler@amd.com>,
Alvin.Lee2@amd.com, daniel@ffwll.ch, george.shen@amd.com,
Alex Deucher <alexander.deucher@amd.com>,
Leo Ma <hanghong.ma@amd.com>,
Jun.Lei@amd.com, harry.wentland@amd.com,
christian.koenig@amd.com
Subject: [PATCH AUTOSEL 6.4 13/31] drm/amd/display: Fix underflow issue on 175hz timing
Date: Fri, 8 Sep 2023 15:31:42 -0400 [thread overview]
Message-ID: <20230908193201.3462957-13-sashal@kernel.org> (raw)
In-Reply-To: <20230908193201.3462957-1-sashal@kernel.org>
From: Leo Ma <hanghong.ma@amd.com>
[ Upstream commit 735688eb905db529efea0c78466fccc1461c3fde ]
[Why]
Screen underflows happen on 175hz timing for 3 plane overlay case.
[How]
Based on dst y prefetch value clamp to equ or oto for bandwidth
calculation.
Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Acked-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Leo Ma <hanghong.ma@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
.../amd/display/dc/dml/dcn32/display_mode_vba_util_32.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
index 61cc4904ade41..4c645854b263b 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
@@ -3463,6 +3463,7 @@ bool dml32_CalculatePrefetchSchedule(
double TimeForFetchingMetaPTE = 0;
double TimeForFetchingRowInVBlank = 0;
double LinesToRequestPrefetchPixelData = 0;
+ double LinesForPrefetchBandwidth = 0;
unsigned int HostVMDynamicLevelsTrips;
double trip_to_mem;
double Tvm_trips;
@@ -3892,11 +3893,15 @@ bool dml32_CalculatePrefetchSchedule(
TimeForFetchingMetaPTE = Tvm_oto;
TimeForFetchingRowInVBlank = Tr0_oto;
*PrefetchBandwidth = prefetch_bw_oto;
+ /* Clamp to oto for bandwidth calculation */
+ LinesForPrefetchBandwidth = dst_y_prefetch_oto;
} else {
*DestinationLinesForPrefetch = dst_y_prefetch_equ;
TimeForFetchingMetaPTE = Tvm_equ;
TimeForFetchingRowInVBlank = Tr0_equ;
*PrefetchBandwidth = prefetch_bw_equ;
+ /* Clamp to equ for bandwidth calculation */
+ LinesForPrefetchBandwidth = dst_y_prefetch_equ;
}
*DestinationLinesToRequestVMInVBlank = dml_ceil(4.0 * TimeForFetchingMetaPTE / LineTime, 1.0) / 4.0;
@@ -3904,7 +3909,7 @@ bool dml32_CalculatePrefetchSchedule(
*DestinationLinesToRequestRowInVBlank =
dml_ceil(4.0 * TimeForFetchingRowInVBlank / LineTime, 1.0) / 4.0;
- LinesToRequestPrefetchPixelData = *DestinationLinesForPrefetch -
+ LinesToRequestPrefetchPixelData = LinesForPrefetchBandwidth -
*DestinationLinesToRequestVMInVBlank - 2 * *DestinationLinesToRequestRowInVBlank;
#ifdef __DML_VBA_DEBUG__
--
2.40.1
next prev parent reply other threads:[~2023-09-08 19:33 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20230908193201.3462957-1-sashal@kernel.org>
2023-09-08 19:31 ` [PATCH AUTOSEL 6.4 10/31] drm/amd/display: Add stream overhead in BW calculations for 128b/132b Sasha Levin
2023-09-08 19:31 ` [PATCH AUTOSEL 6.4 12/31] drm/amd/display: Read down-spread percentage from lut to adjust dprefclk Sasha Levin
2023-09-08 19:31 ` Sasha Levin [this message]
2023-09-08 19:31 ` [PATCH AUTOSEL 6.4 18/31] drm/amd/display: Use DTBCLK as refclk instead of DPREFCLK Sasha Levin
2023-09-08 19:31 ` [PATCH AUTOSEL 6.4 19/31] drm/amd/display: Blocking invalid 420 modes on HDMI TMDS for DCN31 Sasha Levin
2023-09-08 19:31 ` [PATCH AUTOSEL 6.4 20/31] drm/amd/display: Blocking invalid 420 modes on HDMI TMDS for DCN314 Sasha Levin
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