From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C56A9EEB566 for ; Fri, 8 Sep 2023 19:34:49 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4CA2510E92E; Fri, 8 Sep 2023 19:34:49 +0000 (UTC) Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by gabe.freedesktop.org (Postfix) with ESMTPS id AD0EC10E92D; Fri, 8 Sep 2023 19:34:46 +0000 (UTC) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 641D1B821E2; Fri, 8 Sep 2023 19:34:45 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 97DBCC433B8; Fri, 8 Sep 2023 19:34:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1694201684; bh=6RzTfWrGwILb+/p5HCgUR1NJFNXE8mm1n6DjqIxjDLU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=tK8T+3pkRoCeKwuW6EABx3dK6M0HMlDWvjyE0jx7eodUmfAQMieqqgZAGtxrVfYuR 495RzWSKqZMs+XnBnN7DYq15KKCXU+A2SvDXFCak47txziuELsWqnmjO+Lr1VHKvP5 C57g5co9/1ev2CYR0fy2FCTgNsyhJ9VszNwKJeDcgO7wj7Jw7yS3ZLYkHI1DLGxHJf f7dXDMCbLNtb+zvZNW31VTlKlf31qZLH/IPTgDeEpY7TPTJfIs5VVOvNltOZsyqRdb P38bRGFirrrOVLnr8EXfjGifirUXnWoZ9Lm3kuEorJ9jhiMleCDWkAcLRco2triy0X 5iIWAV/hDljjQ== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Subject: [PATCH AUTOSEL 6.1 09/22] drm/amd/display: Fix underflow issue on 175hz timing Date: Fri, 8 Sep 2023 15:33:53 -0400 Message-Id: <20230908193407.3463368-9-sashal@kernel.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230908193407.3463368-1-sashal@kernel.org> References: <20230908193407.3463368-1-sashal@kernel.org> MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore X-stable-base: Linux 6.1.52 Content-Transfer-Encoding: 8bit X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sasha Levin , Dillon Varone , chris.park@amd.com, amd-gfx@lists.freedesktop.org, Alex Hung , airlied@gmail.com, dri-devel@lists.freedesktop.org, Xinhui.Pan@amd.com, Rodrigo.Siqueira@amd.com, samson.tam@amd.com, nathan@kernel.org, sunpeng.li@amd.com, Daniel Wheeler , Alvin.Lee2@amd.com, daniel@ffwll.ch, george.shen@amd.com, Alex Deucher , Leo Ma , Jun.Lei@amd.com, harry.wentland@amd.com, christian.koenig@amd.com Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" From: Leo Ma [ Upstream commit 735688eb905db529efea0c78466fccc1461c3fde ] [Why] Screen underflows happen on 175hz timing for 3 plane overlay case. [How] Based on dst y prefetch value clamp to equ or oto for bandwidth calculation. Reviewed-by: Dillon Varone Acked-by: Alex Hung Signed-off-by: Leo Ma Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin --- .../amd/display/dc/dml/dcn32/display_mode_vba_util_32.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c index b53feeaf5cf11..23e4be2ad63f9 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c @@ -3454,6 +3454,7 @@ bool dml32_CalculatePrefetchSchedule( double TimeForFetchingMetaPTE = 0; double TimeForFetchingRowInVBlank = 0; double LinesToRequestPrefetchPixelData = 0; + double LinesForPrefetchBandwidth = 0; unsigned int HostVMDynamicLevelsTrips; double trip_to_mem; double Tvm_trips; @@ -3883,11 +3884,15 @@ bool dml32_CalculatePrefetchSchedule( TimeForFetchingMetaPTE = Tvm_oto; TimeForFetchingRowInVBlank = Tr0_oto; *PrefetchBandwidth = prefetch_bw_oto; + /* Clamp to oto for bandwidth calculation */ + LinesForPrefetchBandwidth = dst_y_prefetch_oto; } else { *DestinationLinesForPrefetch = dst_y_prefetch_equ; TimeForFetchingMetaPTE = Tvm_equ; TimeForFetchingRowInVBlank = Tr0_equ; *PrefetchBandwidth = prefetch_bw_equ; + /* Clamp to equ for bandwidth calculation */ + LinesForPrefetchBandwidth = dst_y_prefetch_equ; } *DestinationLinesToRequestVMInVBlank = dml_ceil(4.0 * TimeForFetchingMetaPTE / LineTime, 1.0) / 4.0; @@ -3895,7 +3900,7 @@ bool dml32_CalculatePrefetchSchedule( *DestinationLinesToRequestRowInVBlank = dml_ceil(4.0 * TimeForFetchingRowInVBlank / LineTime, 1.0) / 4.0; - LinesToRequestPrefetchPixelData = *DestinationLinesForPrefetch - + LinesToRequestPrefetchPixelData = LinesForPrefetchBandwidth - *DestinationLinesToRequestVMInVBlank - 2 * *DestinationLinesToRequestRowInVBlank; #ifdef __DML_VBA_DEBUG__ -- 2.40.1