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Tue, 19 Sep 2023 22:18:32 -0500 From: Wayne Lin To: Subject: [PATCH 05/19] drm/amd/display: remove guaranteed viewports limitation for odm Date: Wed, 20 Sep 2023 11:16:10 +0800 Message-ID: <20230920031624.3129206-6-Wayne.Lin@amd.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20230920031624.3129206-1-Wayne.Lin@amd.com> References: <20230920031624.3129206-1-Wayne.Lin@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF0000F0DE:EE_|PH8PR12MB6891:EE_ X-MS-Office365-Filtering-Correlation-Id: e387806a-c990-431e-5a66-08dbb9884ecf X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: uox+9itDGExv8UCry0KSdWU006RCsXpYYinx1obxxxYOiMJP6stB9Pqdg3uNKt/7FqcMsFyK9w8cjo/qImRewKfosY1eoxs/r3RdQsUP4YDnDlDYOAjCGOt0nk/Hh3Nd+31LP4cDwgXtxSOPltM5/mLIeF2a1xclrRmNGQPGljMQYhTzq3Fc9UeqjDNf+zkXJQyz7F6J3JWr7a6DfAQBkzoubrntc8AxZ4aZX2x/TERFpQP5yVG9irg2SGdrE2m2YPBCYMBfGpOGn12vYijrND3NAg5sEaAEvnG6AmaE0+mmYkNktl/1VKnqnFbz+NGHYB0gb1yyFaSts3501yKc1/v1qVUYREdrLESgkY/vQP3cAzAZpMRyeP5tUxRiAkhvqU0d6JY2+qkqIMZj2pbuWTtt3mqlPWbncyaLGNWz3qPLPVYkZWkFWwHpVQ7DVi2DNciMzz9jYk7A5rAqjk0DBGDwf6G/C6Al2fdhONLFCdI8rzWSBrIhT97KNfr1qR3fwPR/RiC5Ptl++rBge8zS80zog+bERZJWf/dgnverb18HpnqwnWB60GDBuTDt1NHJEiP0BIwy1O95jEVzMsz7xs8qlSRWVKSelB7DDVdQxg+ZrJQgqQoFh+Jk7aPXxvWoXdvCvGm+qdVIvWB+N1hmBvhJMk6gJTGoMDh3IQcX1P9+4KbwlAVFESZUdCWO0yB759Lo2nMWALKymMhG0jIru3K4FrlWv3raiJ9vis7tJxEFigs5kioTss25G3PMB6J9GAocYu5MCg3/brs1/RXo6Q== X-Forefront-Antispam-Report: CIP:165.204.84.17; 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Reviewed-by: Aric Cyr Acked-by: Wayne Lin Signed-off-by: Wenjing Liu --- drivers/gpu/drm/amd/display/dc/core/dc.c | 34 ------------------- .../drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 27 --------------- 2 files changed, 61 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index e2dcb836a0f0..a2360dfdc83b 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -3948,40 +3948,6 @@ static bool could_mpcc_tree_change_for_active_pipes(struct dc *dc, *is_plane_addition = true; } } - if (dc->config.enable_windowed_mpo_odm) { - const struct rect *guaranteed_viewport = &stream->src; - const struct rect *surface_src, *surface_dst; - bool are_cur_planes_guaranteed = true; - bool are_new_planes_guaranteed = true; - - for (i = 0; i < cur_stream_status->plane_count; i++) { - surface_src = &cur_stream_status->plane_states[i]->src_rect; - surface_dst = &cur_stream_status->plane_states[i]->dst_rect; - if ((surface_src->height > surface_dst->height && surface_src->height > guaranteed_viewport->height) || - (surface_src->width > surface_dst->width && surface_src->width > guaranteed_viewport->width)) - are_cur_planes_guaranteed = false; - } - - for (i = 0; i < surface_count; i++) { - if (srf_updates[i].scaling_info) { - surface_src = &srf_updates[i].scaling_info->src_rect; - surface_dst = &srf_updates[i].scaling_info->dst_rect; - } else { - surface_src = &srf_updates[i].surface->src_rect; - surface_dst = &srf_updates[i].surface->dst_rect; - } - if ((surface_src->height > surface_dst->height && surface_src->height > guaranteed_viewport->height) || - (surface_src->width > surface_dst->width && surface_src->width > guaranteed_viewport->width)) - are_new_planes_guaranteed = false; - } - - if (are_cur_planes_guaranteed && !are_new_planes_guaranteed) { - force_minimal_pipe_splitting = true; - *is_plane_addition = true; - } else if (!are_cur_planes_guaranteed && are_new_planes_guaranteed) { - force_minimal_pipe_splitting = true; - } - } } for (i = 0; i < dc->res_pool->pipe_count; i++) { diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c index 1f53883d8f56..dcbd38bb3ed1 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c @@ -1267,8 +1267,6 @@ static bool should_allow_odm_power_optimization(struct dc *dc, { struct dc_stream_state *stream = context->streams[0]; struct pipe_slice_table slice_table; - struct dc_plane_state *plane; - struct rect guaranteed_viewport; int i; /* @@ -1333,31 +1331,6 @@ static bool should_allow_odm_power_optimization(struct dc *dc, for (i = 0; i < slice_table.odm_combine_count; i++) if (slice_table.odm_combines[i].slice_count > 1) return false; - - /* up to here we know that a plane with viewport equal to stream - * src can be validated with single DPP pipe. Therefore any - * planes with smaller or equal viewport is guaranteed to work - * regardless of its position and scaling ratio. Also we know - * any plane without downscale ratio greater than 1 should also - * work. Up until DCN3x we still have software limitation that - * doesn't implement a smooth transition between ODM combine and - * MPC combine during plane resizing when we are crossing ODM - * capability boundary. So we are adding this guaranteed - * viewport condition to limit ODM power optimization support - * for only the planes within the guaranteed viewport size. Such - * planes can be supported with ODM power optimization without - * ever the need to transition to MPC combine in any scaling - * ratios and positions. Therefore we cover the software - * limitation of this transition sequence. - */ - guaranteed_viewport = stream->src; - for (i = 0; i < context->stream_status[0].plane_count; i++) { - plane = context->stream_status[0].plane_states[i]; - - if ((plane->src_rect.height > plane->dst_rect.height && plane->src_rect.height > guaranteed_viewport.height) || - (plane->src_rect.width > plane->dst_rect.width && plane->src_rect.width > guaranteed_viewport.width)) - return false; - } } else { /* * the new ODM power optimization feature reduces software -- 2.37.3