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Wed, 24 Jan 2024 11:09:17 -0600 From: To: , , , , Subject: [PATCH 1/3] drm/amd/display: Disable ips before dc interrupt setting Date: Wed, 24 Jan 2024 12:09:04 -0500 Message-ID: <20240124170906.901841-1-Roman.Li@amd.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000989E5:EE_|PH0PR12MB8127:EE_ X-MS-Office365-Filtering-Correlation-Id: e0c9728a-5212-4152-b0f9-08dc1cff3455 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: RDMkZs7QQo3e9fJzvs130B54hfQLM+14rid9UGRQq5aCUueBab58GAps1YDD8CNRF5S2gi3DWlcpkoaolt0SnsO2+m+B+74O+sVLlMxABkXZRrXlK4aF8QtJ5qXRbauZgtonR2TSUE39hvZQQOvygtlry4I/pvU7JZY5BVJ18wh3JSLmWoBl/bw/YJWa7AkV2UiLDtl8IyHuWaxwtpTweQOy61aUjBR3IIADmU0jWhXY+uGJ5oRdV+8t12LtjR+TO935OOwqbWWHuW+vWtIpWN/vEp9VVs+YmGjcg7uI0HMKmPmgkj/liNZkJ0v58TdFl9K+Nm2/++4iOceTqeBULyUGjskiZ2sgMtetmjfmVmDJC4ozZz+5ka6aOflRIO9FDSxvHC+zFpvDe055DOlTxyR1vmKiNNEAudWIA5iAsOLWTGt0lJZ2iYM870sKvitDd69vDEIAuzZNA4QlTo8h9vP3Wwvzh20Yc+tjrQBwLCuijv6SPPaqXIUP3mS7Q+a2GRr+JCNdOwC1XnyPpvXzrUrNBMpLlgS9XAAqyN/O/HHepBBVesVZfW1DNkxucGFwn22AWrx81BaZ6zCDzuLXnQ6dtlkQA122laJR7MOCScvQbF70s1OQXmHV5FBHTh0suvJkpg/R/rFuhdiBzyfCQOcOv2qnP3QSSMyPo4RSniGk3+r92UCjYzocQ0QrsG9oQ74sogQWLvUZXNqvJaJJQWBhSjxeXyIHuzzVtboZM4JXMtGcMPIlVoX1r0+FxaGcuzdDrj8wz20rFF+KprjU+kTvn9ZxLGExcAk0zwdjpIU= X-Forefront-Antispam-Report: CIP:165.204.84.17; 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Ip=[165.204.84.17]; Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000989E5.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB8127 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Broadworth , chiahsuan.chung@amd.com, Sunpeng.Li@amd.com, Rodrigo.Siqueira@amd.com, Roman Li , jerry.zuo@amd.com, hamza.mahfooz@amd.com, wayne.lin@amd.com, Harry.Wentland@amd.com Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" From: Roman Li [Why] While in IPS2 an access to dcn registers is not allowed. If interrupt results in dc call, we should disable IPS. [How] Safeguard register access in IPS2 by disabling idle optimization before calling dc interrupt setting api. Signed-off-by: Roman Li Tested-by: Mark Broadworth --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c index 58b880acb087..3390f0d8420a 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c @@ -711,7 +711,7 @@ static inline int dm_irq_state(struct amdgpu_device *adev, { bool st; enum dc_irq_source irq_source; - + struct dc *dc = adev->dm.dc; struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc_id]; if (!acrtc) { @@ -729,6 +729,9 @@ static inline int dm_irq_state(struct amdgpu_device *adev, st = (state == AMDGPU_IRQ_STATE_ENABLE); + if (dc && dc->caps.ips_support && dc->idle_optimizations_allowed) + dc_allow_idle_optimizations(dc, false); + dc_interrupt_set(adev->dm.dc, irq_source, st); return 0; } -- 2.34.1