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Tue, 12 Mar 2024 04:22:44 -0500 From: Wayne Lin To: CC: , , , , , , , , , , Zhongwei , Nicholas Kazlauskas Subject: [PATCH 18/43] drm/amd/display: To adjust dprefclk by down spread percentage Date: Tue, 12 Mar 2024 17:20:11 +0800 Message-ID: <20240312092036.3283319-19-Wayne.Lin@amd.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20240312092036.3283319-1-Wayne.Lin@amd.com> References: <20240312092036.3283319-1-Wayne.Lin@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain Received-SPF: None (SATLEXMB04.amd.com: Wayne.Lin@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF00003441:EE_|MW4PR12MB7189:EE_ X-MS-Office365-Filtering-Correlation-Id: 78330e43-53c1-4a84-03ee-08dc4275fc61 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: h2lQ+mINMkfP4CL2Sga2arJlqsDMuTjlKhm4QAW8Gjrjq8Eq/dvYzFyMxeHVRm7gs34PJGAxMePhbVB3v3CyEwJ74MqXWmDoEoFX+L0OEfKANWnhE6PFP6kQFzHl/+nYM1EAP7aMKt7V/OEpLUuih8O/Xb11H7IB7d3ZNRfWRjkgGR5D6iXT317lQ+6rtjvEi/l2h0ea5T6ji4SkZuaCvCd4fC+U/F0K+brIKShNrOelSJZ7bQasiXmW+aEB16PAbB0N8vWP/wRVfH/iR9p7AT7pAFmCI/z8W93A0I3VbnAUIRez9E0cF3DXj2t7wit8OUzL81GpmkOrLs36t6O1kji4a6GKFZsPIUv65oLAIoK94B7sNRNEzioBCC4N1+B53wju89o/fG9xOV1fgCYA56/2glkvd/mkMg9lIHmEadlp4NOsC+leICGuiur2pjbCte0eHIXet8kkuQyJAgxkKZLXIvTAMZk4e3liKXci4gZRk+0irmAoET4TvRM3jx/U8DLvM/nAPtVzqNL/iCrxrHDOBN/wcZBiKtY6gkKu6dXADKwn4XUj8MKLBgRcW0ixjx0lXraiEvHf/vSyJYY3CSSpZHtHarVk/V1/lXIHthxVER6eY2fl8F6V6wix76wMnjkdJi6nk7BdXjhi44icZ6SGpWUnoO+N/hUp9jm89CvQhjkwR0C52ARIzlsugYHRe0y0JxAcxOYwCNTuMsbjBcBOiWQ6cf0xvzptykeBLpvnCjUoFfk6ifIEG03NBG02 X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230031)(1800799015)(36860700004)(82310400014)(376005); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Mar 2024 09:22:49.1653 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 78330e43-53c1-4a84-03ee-08dc4275fc61 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF00003441.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB7189 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" From: Zhongwei [Why] OLED panels show no display for large vtotal timings. [How] Check if spread spectrum is enabled and read from lut for spread spectrum percentage. Adjust dprefclk as required. Reviewed-by: Nicholas Kazlauskas Acked-by: Wayne Lin Signed-off-by: Zhongwei --- .../display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c | 50 +++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c index c6030bed95a0..96c3562276f4 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c @@ -73,6 +73,12 @@ #define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL_MASK 0x00000007L #define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_DIV_MASK 0x000F0000L +#define regCLK5_0_CLK5_spll_field_8 0x464b +#define regCLK5_0_CLK5_spll_field_8_BASE_IDX 0 + +#define CLK5_0_CLK5_spll_field_8__spll_ssc_en__SHIFT 0xd +#define CLK5_0_CLK5_spll_field_8__spll_ssc_en_MASK 0x00002000L + #define REG(reg_name) \ (ctx->clk_reg_offsets[reg ## reg_name ## _BASE_IDX] + reg ## reg_name) @@ -410,6 +416,17 @@ static void dcn35_dump_clk_registers(struct clk_state_registers_and_bypass *regs { } +static bool dcn35_is_spll_ssc_enabled(struct clk_mgr *clk_mgr_base) +{ + struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); + struct dc_context *ctx = clk_mgr->base.ctx; + uint32_t ssc_enable; + + REG_GET(CLK5_0_CLK5_spll_field_8, spll_ssc_en, &ssc_enable); + + return ssc_enable == 1; +} + static void init_clk_states(struct clk_mgr *clk_mgr) { uint32_t ref_dtbclk = clk_mgr->clks.ref_dtbclk_khz; @@ -424,7 +441,16 @@ static void init_clk_states(struct clk_mgr *clk_mgr) void dcn35_init_clocks(struct clk_mgr *clk_mgr) { + struct clk_mgr_internal *clk_mgr_int = TO_CLK_MGR_INTERNAL(clk_mgr); init_clk_states(clk_mgr); + + // to adjust dp_dto reference clock if ssc is enable otherwise to apply dprefclk + if (dcn35_is_spll_ssc_enabled(clk_mgr)) + clk_mgr->dp_dto_source_clock_in_khz = + dce_adjust_dp_ref_freq_for_ss(clk_mgr_int, clk_mgr->dprefclk_khz); + else + clk_mgr->dp_dto_source_clock_in_khz = clk_mgr->dprefclk_khz; + } static struct clk_bw_params dcn35_bw_params = { .vram_type = Ddr4MemType, @@ -513,6 +539,28 @@ static DpmClocks_t_dcn35 dummy_clocks; static struct dcn35_watermarks dummy_wms = { 0 }; +static struct dcn35_ss_info_table ss_info_table = { + .ss_divider = 1000, + .ss_percentage = {0, 0, 375, 375, 375} +}; + +static void dcn35_read_ss_info_from_lut(struct clk_mgr_internal *clk_mgr) +{ + struct dc_context *ctx = clk_mgr->base.ctx; + uint32_t clock_source; + + REG_GET(CLK1_CLK2_BYPASS_CNTL, CLK2_BYPASS_SEL, &clock_source); + + if (dcn35_is_spll_ssc_enabled(&clk_mgr->base) && (clock_source < ARRAY_SIZE(ss_info_table.ss_percentage))) { + clk_mgr->dprefclk_ss_percentage = ss_info_table.ss_percentage[clock_source]; + + if (clk_mgr->dprefclk_ss_percentage != 0) { + clk_mgr->ss_on_dprefclk = true; + clk_mgr->dprefclk_ss_divider = ss_info_table.ss_divider; + } + } +} + static void dcn35_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn35_watermarks *table) { int i, num_valid_sets; @@ -1057,6 +1105,8 @@ void dcn35_clk_mgr_construct( dce_clock_read_ss_info(&clk_mgr->base); /*when clk src is from FCH, it could have ss, same clock src as DPREF clk*/ + dcn35_read_ss_info_from_lut(&clk_mgr->base); + clk_mgr->base.base.bw_params = &dcn35_bw_params; if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) { -- 2.37.3