From: Lang Yu <Lang.Yu@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: Alex Deucher <alexander.deucher@amd.com>,
Christian Koenig <christian.koenig@amd.com>,
Veerabadhran Gopalakrishnan <Veerabadhran.Gopalakrishnan@amd.com>,
Lang Yu <Lang.Yu@amd.com>
Subject: [PATCH 2/2] drm/amdgpu/umsch: reinitialize write pointer in hw init
Date: Mon, 25 Mar 2024 13:37:23 +0800 [thread overview]
Message-ID: <20240325053723.3183224-1-Lang.Yu@amd.com> (raw)
Otherwise the old one will be used during GPU reset.
That's not expected.
Signed-off-by: Lang Yu <Lang.Yu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c b/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c
index 84368cf1e175..bd57896ab85d 100644
--- a/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c
@@ -225,6 +225,8 @@ static int umsch_mm_v4_0_ring_start(struct amdgpu_umsch_mm *umsch)
WREG32_SOC15(VCN, 0, regVCN_UMSCH_RB_SIZE, ring->ring_size);
+ ring->wptr = 0;
+
data = RREG32_SOC15(VCN, 0, regVCN_RB_ENABLE);
data &= ~(VCN_RB_ENABLE__AUDIO_RB_EN_MASK);
WREG32_SOC15(VCN, 0, regVCN_RB_ENABLE, data);
--
2.25.1
next reply other threads:[~2024-03-25 5:37 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-25 5:37 Lang Yu [this message]
2024-03-26 3:22 ` [PATCH 2/2] drm/amdgpu/umsch: reinitialize write pointer in hw init Xu, Feifei
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