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Thu, 28 Mar 2024 04:40:29 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CH3PEPF00000010.mail.protection.outlook.com (10.167.244.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7409.10 via Frontend Transport; Thu, 28 Mar 2024 04:40:29 +0000 Received: from lang-desktop.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 27 Mar 2024 23:40:27 -0500 From: Lang Yu To: CC: Alex Deucher , Christian Koenig , Lang Yu Subject: [PATCH] drm/amdgpu: add post reset IP callback Date: Thu, 28 Mar 2024 12:40:14 +0800 Message-ID: <20240328044014.3278891-1-Lang.Yu@amd.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF00000010:EE_|PH7PR12MB7817:EE_ X-MS-Office365-Filtering-Correlation-Id: d21932c8-38ba-46ef-8071-08dc4ee13209 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Mar 2024 04:40:29.3233 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d21932c8-38ba-46ef-8071-08dc4ee13209 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF00000010.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7817 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" There are use cases which need full GPU functionality (e.g., VM update, TLB inavildate) when doing a GPU reset. Especially, the mes/umsch self tests which help validate the hw state after hw init like ring/ib tests. Add a post reset IP callback to handle such use cases which will be executed after GPU reset succeeds. Signed-off-by: Lang Yu --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 24 ++++++++++++++++++++++ drivers/gpu/drm/amd/include/amd_shared.h | 3 +++ 2 files changed, 27 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 12dc71a6b5db..feeab9397aab 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -5556,6 +5556,27 @@ static int amdgpu_device_health_check(struct list_head *device_list_handle) return ret; } +static int amdgpu_device_ip_post_reset(struct amdgpu_device *adev) +{ + uint32_t i; + int r; + + for (i = 0; i < adev->num_ip_blocks; i++) { + if (!adev->ip_blocks[i].status.valid || + !adev->ip_blocks[i].version->funcs->post_reset) + continue; + + r = adev->ip_blocks[i].version->funcs->post_reset(adev); + if (r) { + DRM_ERROR("post reset of IP block <%s> failed %d\n", + adev->ip_blocks[i].version->funcs->name, r); + return r; + } + } + + return r; +} + /** * amdgpu_device_gpu_recover - reset the asic and recover scheduler * @@ -5805,6 +5826,9 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev, amdgpu_put_xgmi_hive(hive); } + if (!r && !job_signaled) + r = amdgpu_device_ip_post_reset(adev); + if (r) dev_info(adev->dev, "GPU reset end with ret = %d\n", r); diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h index b0a6256e89f4..33ce30a8e3ab 100644 --- a/drivers/gpu/drm/amd/include/amd_shared.h +++ b/drivers/gpu/drm/amd/include/amd_shared.h @@ -287,6 +287,7 @@ enum amd_dpm_forced_level; * @pre_soft_reset: pre soft reset the IP block * @soft_reset: soft reset the IP block * @post_soft_reset: post soft reset the IP block + * @post_reset: handles IP specific post reset stuff(e.g., self test) * @set_clockgating_state: enable/disable cg for the IP block * @set_powergating_state: enable/disable pg for the IP block * @get_clockgating_state: get current clockgating status @@ -316,11 +317,13 @@ struct amd_ip_funcs { int (*pre_soft_reset)(void *handle); int (*soft_reset)(void *handle); int (*post_soft_reset)(void *handle); + int (*post_reset)(void *handle); int (*set_clockgating_state)(void *handle, enum amd_clockgating_state state); int (*set_powergating_state)(void *handle, enum amd_powergating_state state); void (*get_clockgating_state)(void *handle, u64 *flags); + }; -- 2.25.1