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Tue, 30 Jul 2024 02:22:19 -0500 From: Wayne Lin To: CC: , , , , , , , , , , Dillon Varone , Alvin Lee Subject: [PATCH 21/22] drm/amd/display: Add DML2.1 option to disable DRR clamped P-State Strategies Date: Tue, 30 Jul 2024 15:18:42 +0800 Message-ID: <20240730071843.880430-22-Wayne.Lin@amd.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20240730071843.880430-1-Wayne.Lin@amd.com> References: <20240730071843.880430-1-Wayne.Lin@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain Received-SPF: None (SATLEXMB04.amd.com: Wayne.Lin@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF00026368:EE_|IA0PR12MB8227:EE_ X-MS-Office365-Filtering-Correlation-Id: 567dacda-7917-466b-73be-08dcb0685d4e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|82310400026|376014|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?XgEW0g2zJi9u6ENzIzSt+5wpeGG5woLz4KVVZnLb/kRYAFVX4wYWXm0Xovfu?= =?us-ascii?Q?7FZo9GBGGcgyooPlU2k3rvJRIU1pFvtfLPvL42WVDnMZUJVLSJ2n8OqgZh/Z?= =?us-ascii?Q?NfsS4gMAhfW9SMxRvZSF73YtdvPWpGP/IdVk11j+gO8WtZEOKBIwjnr1b/B5?= =?us-ascii?Q?uMTqYQVqdJK7TQovNDzXH0SJMgPoXfIlA+EMRlLtknKkdA+qYG/0kbcArUGV?= =?us-ascii?Q?a6iMK9C8wvMPSo82L8AfuL3goHvqDZrI6olCN3Z1EgU/kKVrNGNSxXMHaMzq?= =?us-ascii?Q?ujPkto0Me+TKT1/Vy24LMZ8kbyvbxbXxcy0BJbx/uJ7xFVqqPWxb+q4EpN+p?= =?us-ascii?Q?zAh0UeemQKpMhJCRZGxlEkRaG6wrPXBCDVm9cIJSpPE3MTIQJKk/BOED8KEW?= =?us-ascii?Q?pJqWCP/YU12qTP3wDuhbGFSzN43UAW2kE3AdcqSaSMBTFHNIQZ0fBzUBKSf9?= =?us-ascii?Q?Rd4kPm45YJS9F8aCiNIOXSfa+cSEwk71ZIB3UHju0NpSuKHUrQozrlUD2OIx?= =?us-ascii?Q?Y6YJLw4xNx0cWJ54PBnSszENMAwZizsqwmVVxwmEyLSDCF0fgtkpRPVuSa+g?= =?us-ascii?Q?e8BpFUxPnUUktRf8ODEFamEBsNtwL43io2/0zc5uyWnCbwKfIbFA9bzx09nG?= =?us-ascii?Q?6AlM/jbYnnmBeGxwf7/ldLWAzmn32Q42228wstEJneuePB859w/wigkOka6Q?= =?us-ascii?Q?9N3qmZ8VJ5Ppr4NWEX9/LRZaEAp7IlJGgKMaYuCG5G4nNJCJ3gym1gnD/W67?= =?us-ascii?Q?J2rG7UXBLtU95hw8BMJMSZ2hHYAV+B+ogKm5CZingTvOsP8YeaAbcd7z68yF?= =?us-ascii?Q?YqKStxvu0ELog8fsiVklpSbr5Scu8HtoYAqCsFssl6/in6n2lw5ZE85DTVcB?= =?us-ascii?Q?lNQpQW1NsALDJedeyCKrS3bpZ892B0eQM2nkaHtGGNY64PI9g+51rCkDztFF?= =?us-ascii?Q?O2lFVmIKi8MxUar4l8a6VlRyoc0I8ptsJORQtI1AZ6ZCzBAaVmxDP88AYqRc?= =?us-ascii?Q?SuEzIYBwnxsbnjtTiewg1Id+Eu6OPsOR1CsOji68IDrLSjhBjD/zUUVt2fAv?= =?us-ascii?Q?HNw2r6jL+itNmoymh561tp2Paxq7gxUXx/Rsxj/gdxSDytKHJ/SK6+dese+v?= =?us-ascii?Q?Mq5qmyftmoFttkoNlzhFhuTi7nkc/DsVZD6DGm6xfM4Eeiu2PA/x/WnInPa8?= =?us-ascii?Q?V9nBzFe1FzHKal/UZsE8Yq8rsT/M1pFQsf3D76QbfXHosvEq3+QOY/qjDVRJ?= =?us-ascii?Q?HCsCY9+M2dPLpnX60udH1AKemKlJ/OOIYQm8DXCrYhqZDR7Lf2PkQT9cmU6N?= =?us-ascii?Q?N576PLt7blz0vEVJeC4u8LKrOZ7c2KumywiQadfHTPV+2aDxVRu2ZfuPCqN1?= =?us-ascii?Q?IiHjjLZh8WVLCIdDA8gQHTRbyG8vqF0j1GKNf/Q6artSqD2lYjRYWcJ1Az7G?= =?us-ascii?Q?EdYMXXSoi38dFt8LAZb8Tt1x3GARC/CW?= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(1800799024)(82310400026)(376014)(36860700013); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jul 2024 07:22:26.7340 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 567dacda-7917-466b-73be-08dcb0685d4e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF00026368.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8227 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" From: Dillon Varone [WHY & HOW] When DRR is active with variable refresh rate, add the ability to block DRR clamped P-State strategies (such as SubVP). Reviewed-by: Alvin Lee Signed-off-by: Dillon Varone Signed-off-by: Wayne Lin --- drivers/gpu/drm/amd/display/dc/dc.h | 1 + drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c | 4 +++- .../gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h | 1 + .../dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c | 7 +++++-- 4 files changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index b6a5ea93fd45..49725f06a2d5 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -511,6 +511,7 @@ enum in_game_fams_config { INGAME_FAMS_SINGLE_DISP_ENABLE, // enable in-game fams INGAME_FAMS_DISABLE, // disable in-game fams INGAME_FAMS_MULTI_DISP_ENABLE, //enable in-game fams for multi-display + INGAME_FAMS_MULTI_DISP_CLAMPED_ONLY, //enable in-game fams for multi-display only for clamped RR strategies }; /** diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c index 41ecf00ed196..d35dd507cb9f 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c @@ -66,7 +66,9 @@ static void dml21_apply_debug_options(const struct dc *in_dc, struct dml2_contex disable_fams2; pmo_options->disable_fams2 = disable_fams2; - pmo_options->disable_drr_var_when_var_active = in_dc->debug.disable_fams_gaming; + pmo_options->disable_drr_var_when_var_active = in_dc->debug.disable_fams_gaming == INGAME_FAMS_DISABLE || + in_dc->debug.disable_fams_gaming == INGAME_FAMS_MULTI_DISP_CLAMPED_ONLY; + pmo_options->disable_drr_clamped_when_var_active = in_dc->debug.disable_fams_gaming == INGAME_FAMS_DISABLE; } static void dml21_init(const struct dc *in_dc, struct dml2_context **dml_ctx, const struct dml2_configuration_options *config) diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h b/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h index a824ce56c54e..1c773bbb9992 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h @@ -74,6 +74,7 @@ struct dml2_pmo_options { bool disable_drr_var; bool disable_drr_clamped; bool disable_drr_var_when_var_active; + bool disable_drr_clamped_when_var_active; bool disable_fams2; bool disable_vactive_det_fill_bw_pad; /* dml2_project_dcn4x_stage2_auto_drr_svp and above only */ bool disable_dyn_odm; diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c index 9c6397aafd38..06e786995390 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c @@ -1441,8 +1441,11 @@ static bool stream_matches_drr_policy(struct dml2_pmo_instance *pmo, strategy_matches_drr_requirements = false; } else if (is_bit_set_in_bitfield(PMO_DRR_CLAMPED_STRATEGY_MASK, stream_pstate_method) && (pmo->options->disable_drr_clamped || - !stream_descriptor->timing.drr_config.enabled || - (!stream_descriptor->timing.drr_config.drr_active_fixed && !stream_descriptor->timing.drr_config.drr_active_variable))) { + (!stream_descriptor->timing.drr_config.enabled || + (!stream_descriptor->timing.drr_config.drr_active_fixed && !stream_descriptor->timing.drr_config.drr_active_variable)) || + (pmo->options->disable_drr_clamped_when_var_active && + stream_descriptor->timing.drr_config.enabled && + stream_descriptor->timing.drr_config.drr_active_variable))) { /* DRR fixed strategies are disallowed due to settings or policy */ strategy_matches_drr_requirements = false; } else if (is_bit_set_in_bitfield(PMO_FW_STRATEGY_MASK, stream_pstate_method) && -- 2.37.3