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CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB03.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(36860700013)(376014)(1800799024)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Sep 2024 20:06:54.9648 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0bbe7661-be1f-4f72-cc0a-08dcd10af3d6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397B1.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8689 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" This patch series introduces base code of AMDGPU usermode queues for gfx workloads. Usermode queues is a method of GPU workload submission into the graphics hardware without any interaction with kernel/DRM schedulers. In this method, a userspace graphics application can create its own workqueue and submit it directly in the GPU HW. The general idea of how Userqueues are supposed to work: - The application creates the following GPU objetcs: - A queue object to hold the workload packets. - A read pointer object. - A write pointer object. - A doorbell page. - Other supporting buffer objects as per target IP engine (shadow, GDS etc, information available with AMDGPU_INFO_IOCTL) - The application picks a 32-bit offset in the doorbell page for this queue. - The application uses the usermode_queue_create IOCTL introduced in this patch, by passing the GPU addresses of these objects (read ptr, write ptr, queue base address, shadow, gds) with doorbell object and 32-bit doorbell offset in the doorbell page. - The kernel creates the queue and maps it in the HW. - The application maps the GPU buffers in process address space. - The application can start submitting the data in the queue as soon as the kernel IOCTL returns. - After filling the workload data in the queue, the app must write the number of dwords added in the queue into the doorbell offset and the WPTR buffer. The GPU will start fetching the data as soon as its done. - This series adds usermode queue support for all three MES based IPs (GFX, SDMA and Compute). - This series also adds eviction fences to handle migration of the userqueue mapped buffers by TTM. - For synchronization of userqueues, we have added a secure semaphores IOCTL which is getting reviewed separately here: https://patchwork.freedesktop.org/patch/611971/ libDRM UAPI changes for this series can be found here: (This also contains an example test utility which demonstrates the usage of userqueue UAPI) https://gitlab.freedesktop.org/mesa/drm/-/merge_requests/287 MESA changes consuming this series can be seen in the MR here: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29010 Alex Deucher (1): drm/amdgpu: UAPI for user queue management Arvind Yadav (4): drm/amdgpu: enable SDMA usermode queues drm/amdgpu: Add input fence to sync bo unmap drm/amdgpu: fix MES GFX mask Revert "drm/amdgpu: don't allow userspace to create a doorbell BO" Shashank Sharma (18): drm/amdgpu: add usermode queue base code drm/amdgpu: add new IOCTL for usermode queue drm/amdgpu: add helpers to create userqueue object drm/amdgpu: create MES-V11 usermode queue for GFX drm/amdgpu: create context space for usermode queue drm/amdgpu: map usermode queue into MES drm/amdgpu: map wptr BO into GART drm/amdgpu: generate doorbell index for userqueue drm/amdgpu: cleanup leftover queues drm/amdgpu: enable GFX-V11 userqueue support drm/amdgpu: enable compute/gfx usermode queue drm/amdgpu: update userqueue BOs and PDs drm/amdgpu: add kernel config for gfx-userqueue drm/amdgpu: add gfx eviction fence helpers drm/amdgpu: add userqueue suspend/resume functions drm/amdgpu: suspend gfx userqueues drm/amdgpu: resume gfx userqueues Revert "drm/amdgpu/gfx11: only enable CP GFX shadowing on SR-IOV" drivers/gpu/drm/amd/amdgpu/Kconfig | 8 + drivers/gpu/drm/amd/amdgpu/Makefile | 10 +- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 11 +- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5 +- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 10 + .../drm/amd/amdgpu/amdgpu_eviction_fence.c | 297 ++++++++ .../drm/amd/amdgpu/amdgpu_eviction_fence.h | 67 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 68 +- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 11 + drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 3 - drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 2 +- .../gpu/drm/amd/amdgpu/amdgpu_userq_fence.c | 713 ++++++++++++++++++ .../gpu/drm/amd/amdgpu/amdgpu_userq_fence.h | 74 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c | 644 ++++++++++++++++ drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 42 +- drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 16 +- .../gpu/drm/amd/amdgpu/mes_v11_0_userqueue.c | 395 ++++++++++ .../gpu/drm/amd/amdgpu/mes_v11_0_userqueue.h | 30 + drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 5 + .../gpu/drm/amd/include/amdgpu_userqueue.h | 100 +++ drivers/gpu/drm/amd/include/v11_structs.h | 4 +- include/uapi/drm/amdgpu_drm.h | 252 +++++++ 22 files changed, 2722 insertions(+), 45 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.c create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.h create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.h create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c create mode 100644 drivers/gpu/drm/amd/amdgpu/mes_v11_0_userqueue.c create mode 100644 drivers/gpu/drm/amd/amdgpu/mes_v11_0_userqueue.h create mode 100644 drivers/gpu/drm/amd/include/amdgpu_userqueue.h -- 2.45.1