From: Wayne Lin <Wayne.Lin@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: Harry Wentland <harry.wentland@amd.com>,
Leo Li <sunpeng.li@amd.com>,
Rodrigo Siqueira <rodrigo.siqueira@amd.com>,
Hamza Mahfooz <hamza.mahfooz@amd.com>,
Aurabindo Pillai <aurabindo.pillai@amd.com>,
"Roman Li" <roman.li@amd.com>, Wayne Lin <wayne.lin@amd.com>,
Tom Chung <chiahsuan.chung@amd.com>,
Fangzhi Zuo <jerry.zuo@amd.com>,
Zaeem Mohamed <zaeem.mohamed@amd.com>,
Solomon Chiu <solomon.chiu@amd.com>,
Daniel Wheeler <daniel.wheeler@amd.com>,
Yihan Zhu <Yihan.Zhu@amd.com>,
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Subject: [PATCH 02/10] drm/amd/display: w/a to program DISPCLK_R_GATE_DISABLE DCN35
Date: Tue, 15 Oct 2024 16:17:05 +0800 [thread overview]
Message-ID: <20241015081713.3042665-3-Wayne.Lin@amd.com> (raw)
In-Reply-To: <20241015081713.3042665-1-Wayne.Lin@amd.com>
From: Yihan Zhu <Yihan.Zhu@amd.com>
[WHY & HOW]
Cursor corruption observed on USBC display with specific system setup with a
reboot. Cursor memory might still in the lightsleep state due to voltage
issue, we need program DISPCLK_R_GATE_DISABLE to avoid this issue only on
DCN35.
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Yihan Zhu <Yihan.Zhu@amd.com>
Signed-off-by: Wayne Lin <wayne.lin@amd.com>
---
.../drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h | 1 +
.../drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h | 1 +
.../drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c | 22 +++++++++++++++----
3 files changed, 20 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h b/drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
index cd1706d301e7..f09cba8e29cc 100644
--- a/drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
@@ -690,6 +690,7 @@ struct dcn20_dpp {
int lb_memory_size;
int lb_bits_per_entry;
bool is_write_to_ram_a_safe;
+ bool dispclk_r_gate_disable;
struct scaler_data scl_data;
struct pwl_params pwl_data;
};
diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
index b110f35ef66b..f236824126e9 100644
--- a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
@@ -572,6 +572,7 @@ struct dcn3_dpp {
int lb_memory_size;
int lb_bits_per_entry;
bool is_write_to_ram_a_safe;
+ bool dispclk_r_gate_disable;
struct scaler_data scl_data;
struct pwl_params pwl_data;
};
diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c
index 9f885a03eec6..62b7012cda43 100644
--- a/drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c
@@ -50,11 +50,21 @@ void dpp35_dppclk_control(
DPPCLK_RATE_CONTROL, dppclk_div,
DPP_CLOCK_ENABLE, 1);
else
- REG_UPDATE(DPP_CONTROL,
- DPP_CLOCK_ENABLE, 1);
+ if (dpp->dispclk_r_gate_disable)
+ REG_UPDATE_2(DPP_CONTROL,
+ DPP_CLOCK_ENABLE, 1,
+ DISPCLK_R_GATE_DISABLE, 1);
+ else
+ REG_UPDATE(DPP_CONTROL,
+ DPP_CLOCK_ENABLE, 1);
} else
- REG_UPDATE(DPP_CONTROL,
- DPP_CLOCK_ENABLE, 0);
+ if (dpp->dispclk_r_gate_disable)
+ REG_UPDATE_2(DPP_CONTROL,
+ DPP_CLOCK_ENABLE, 0,
+ DISPCLK_R_GATE_DISABLE, 0);
+ else
+ REG_UPDATE(DPP_CONTROL,
+ DPP_CLOCK_ENABLE, 0);
}
void dpp35_program_bias_and_scale_fcnv(
@@ -126,6 +136,10 @@ bool dpp35_construct(
(const struct dcn3_dpp_mask *)(tf_mask));
dpp->base.funcs = &dcn35_dpp_funcs;
+
+ // w/a for cursor memory stuck in LS by programming DISPCLK_R_GATE_DISABLE, limit w/a to some ASIC revs
+ if (dpp->base.ctx->asic_id.hw_internal_rev <= 0x10)
+ dpp->dispclk_r_gate_disable = true;
return ret;
}
--
2.37.3
next prev parent reply other threads:[~2024-10-15 8:17 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-15 8:17 [PATCH 00/10] DC Patches October 14, 2024 Wayne Lin
2024-10-15 8:17 ` [PATCH 01/10] drm/amd/display: temp w/a for dGPU to enter idle optimizations Wayne Lin
2024-10-15 13:14 ` Mario Limonciello
2024-10-16 13:13 ` Pillai, Aurabindo
2024-10-16 13:15 ` Mario Limonciello
2024-10-15 8:17 ` Wayne Lin [this message]
2024-10-15 8:17 ` [PATCH 03/10] drm/amd/display: Reuse subvp enable check for DCN401 Wayne Lin
2024-10-15 8:17 ` [PATCH 04/10] drm/amd/display: Adding array index check to prevent memory corruption Wayne Lin
2024-10-15 8:17 ` [PATCH 05/10] drm/amd/display: temp w/a for DP Link Layer compliance Wayne Lin
2024-10-15 8:17 ` [PATCH 06/10] drm/amd/display: Recalculate SubVP Phantom VBlank End in dml21 Wayne Lin
2024-10-15 8:17 ` [PATCH 07/10] drm/amd/display: Add a Precise Delay Routine Wayne Lin
2024-10-15 8:17 ` [PATCH 08/10] drm/amd/display: update fullscreen status to SPL Wayne Lin
2024-10-15 8:17 ` [PATCH 09/10] drm/amd/display: To change dcn301_init.h guard Wayne Lin
2024-10-15 8:17 ` [PATCH 10/10] drm/amd/display: 3.2.306 Wayne Lin
2024-10-17 18:44 ` [PATCH 00/10] DC Patches October 14, 2024 Wheeler, Daniel
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