From: Alexandre Demers <alexandre.f.demers@gmail.com>
To: amd-gfx@lists.freedesktop.org
Subject: [PATCH 6/6] drm/amdgpu: add defines for pin_offsets in DCE8
Date: Thu, 27 Feb 2025 00:22:41 -0500 [thread overview]
Message-ID: <20250227052241.171102-7-alexandre.f.demers@gmail.com> (raw)
In-Reply-To: <20250227052241.171102-1-alexandre.f.demers@gmail.com>
Define pin_offsets values in the same way it is done in DCE8
Signed-off-by: Alexandre Demers <alexandre.f.demers@gmail.com>
---
drivers/gpu/drm/amd/amdgpu/cikd.h | 9 +++++++++
drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 14 +++++++-------
2 files changed, 16 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/cikd.h b/drivers/gpu/drm/amd/amdgpu/cikd.h
index 06088d52d81c..279288365940 100644
--- a/drivers/gpu/drm/amd/amdgpu/cikd.h
+++ b/drivers/gpu/drm/amd/amdgpu/cikd.h
@@ -51,6 +51,15 @@
#define HPD4_REGISTER_OFFSET (0x1813 - 0x1807)
#define HPD5_REGISTER_OFFSET (0x1816 - 0x1807)
+/* audio endpt instance offsets */
+#define AUD0_REGISTER_OFFSET (0x1780 - 0x1780)
+#define AUD1_REGISTER_OFFSET (0x1786 - 0x1780)
+#define AUD2_REGISTER_OFFSET (0x178c - 0x1780)
+#define AUD3_REGISTER_OFFSET (0x1792 - 0x1780)
+#define AUD4_REGISTER_OFFSET (0x1798 - 0x1780)
+#define AUD5_REGISTER_OFFSET (0x179d - 0x1780)
+#define AUD6_REGISTER_OFFSET (0x17a4 - 0x1780)
+
#define BONAIRE_GB_ADDR_CONFIG_GOLDEN 0x12010001
#define HAWAII_GB_ADDR_CONFIG_GOLDEN 0x12011003
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
index 04b79ff87f75..5e657b43a159 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
@@ -1395,13 +1395,13 @@ static void dce_v8_0_audio_enable(struct amdgpu_device *adev,
}
static const u32 pin_offsets[7] = {
- (0x1780 - 0x1780),
- (0x1786 - 0x1780),
- (0x178c - 0x1780),
- (0x1792 - 0x1780),
- (0x1798 - 0x1780),
- (0x179d - 0x1780),
- (0x17a4 - 0x1780),
+ AUD0_REGISTER_OFFSET,
+ AUD1_REGISTER_OFFSET,
+ AUD2_REGISTER_OFFSET,
+ AUD3_REGISTER_OFFSET,
+ AUD4_REGISTER_OFFSET,
+ AUD5_REGISTER_OFFSET,
+ AUD6_REGISTER_OFFSET,
};
static int dce_v8_0_audio_init(struct amdgpu_device *adev)
--
2.48.1
prev parent reply other threads:[~2025-02-27 5:23 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-27 5:22 [PATCH 0/6] add missing DCE6 functions and uniformize value definitions Alexandre Demers
2025-02-27 5:22 ` [PATCH 1/6] drm/amdgpu: add or move defines for DCE6 in sid.h Alexandre Demers
2025-02-27 5:22 ` [PATCH 2/6] drm/amdgpu: add dce_v6_0_soft_reset() to DCE6 Alexandre Demers
2025-02-27 14:23 ` Alex Deucher
2025-02-27 18:51 ` Alexandre Demers
2025-02-27 19:01 ` Alex Deucher
2025-02-27 19:05 ` Alex Deucher
2025-02-27 19:11 ` Alexandre Demers
2025-02-28 14:32 ` Alex Deucher
2025-02-27 19:09 ` Alexandre Demers
2025-02-27 5:22 ` [PATCH 3/6] drm/amdgpu: complete dce_v6_0_set_crtc_vline_interrupt_state() in DCE6 Alexandre Demers
2025-02-27 14:22 ` Alex Deucher
2025-02-27 5:22 ` [PATCH 4/6] drm/amdgpu: add some comments " Alexandre Demers
2025-02-27 5:22 ` [PATCH 5/6] dmr/amdgpu: fix style " Alexandre Demers
2025-02-27 5:22 ` Alexandre Demers [this message]
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