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Wed, 2 Apr 2025 04:14:39 -0500 Received: from JesseDEV.guestwireless.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.39 via Frontend Transport; Wed, 2 Apr 2025 04:14:32 -0500 From: "Jesse.zhang@amd.com" To: CC: , Christian Koenig , , , "Jesse.zhang@amd.com" , Jesse Zhang Subject: [v3 4/7] drm/amd/amdgpu: Refactor SDMA v5.0 reset logic into stop_queue and restore_queue functions Date: Wed, 2 Apr 2025 17:14:03 +0800 Message-ID: <20250402091406.1641643-4-jesse.zhang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250402091406.1641643-1-jesse.zhang@amd.com> References: <20250402091406.1641643-1-jesse.zhang@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9DB:EE_|CY8PR12MB8412:EE_ X-MS-Office365-Filtering-Correlation-Id: 99747ac8-51dc-4290-6545-08dd71c6ccdc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB03.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(82310400026)(1800799024)(36860700013)(376014); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Apr 2025 09:14:40.9531 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 99747ac8-51dc-4290-6545-08dd71c6ccdc X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9DB.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB8412 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" From: "Jesse.zhang@amd.com" This patch refactors the SDMA v5.0 reset logic by splitting the `sdma_v5_0_reset_queue` function into two separate functions: `sdma_v5_0_stop_queue` and `sdma_v5_0_restore_queue`. This change aligns with the new SDMA reset mechanism, where the reset process is divided into stopping the queue, performing the reset, and restoring the queue. 1. **Split `sdma_v5_0_reset_queue`**: - Extracted the queue stopping logic into `sdma_v5_0_stop_queue`. - Extracted the queue restoration logic into `sdma_v5_0_restore_queue`. - The soft reset step is now handled by the caller (`amdgpu_sdma_reset_engine`). 2. **Update Ring Functions**: - Added `stop_queue` and `start_queue` to the `sdma_v5_0_ring_funcs` structure to support the new reset mechanism. v2: remove the suspend_user_queues param when calling amdgpu_sdma_reset_engine() v3: Update stop_queue/start_queue function paramters to use ring pointer instead of device/instance(Christian) Signed-off-by: Jesse Zhang --- drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 41 ++++++++++++++++---------- 1 file changed, 26 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c index 9501652f903d..cd2d4c2af77e 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c @@ -1508,17 +1508,25 @@ static int sdma_v5_0_soft_reset(struct amdgpu_ip_block *ip_block) static int sdma_v5_0_reset_queue(struct amdgpu_ring *ring, unsigned int vmid) { struct amdgpu_device *adev = ring->adev; - int j, r; - u32 f32_cntl, freeze, cntl, preempt, soft_reset, stat1_reg; - u32 inst_id; + u32 inst_id = ring->me; + + return amdgpu_sdma_reset_engine(adev, inst_id); +} + +static int sdma_v5_0_stop_queue(struct amdgpu_ring *ring) +{ + int j, r = 0; + u32 f32_cntl, freeze, cntl, preempt, stat1_reg; + struct amdgpu_device *adev = ring->adev; + u32 inst_id = ring->me; if (amdgpu_sriov_vf(adev)) return -EINVAL; - inst_id = ring->me; + amdgpu_gfx_rlc_enter_safe_mode(adev, 0); /* stop queue */ - sdma_v5_0_gfx_stop(adev, 1 << ring->me); + sdma_v5_0_gfx_stop(adev, inst_id); /* engine stop SDMA1_F32_CNTL.HALT to 1 and SDMAx_FREEZE freeze bit to 1 */ freeze = RREG32(sdma_v5_0_get_reg_offset(adev, inst_id, mmSDMA0_FREEZE)); @@ -1554,17 +1562,19 @@ static int sdma_v5_0_reset_queue(struct amdgpu_ring *ring, unsigned int vmid) preempt = RREG32(sdma_v5_0_get_reg_offset(adev, inst_id, mmSDMA0_GFX_PREEMPT)); preempt = REG_SET_FIELD(preempt, SDMA0_GFX_PREEMPT, IB_PREEMPT, 0); WREG32(sdma_v5_0_get_reg_offset(adev, inst_id, mmSDMA0_GFX_PREEMPT), preempt); +err0: + amdgpu_gfx_rlc_exit_safe_mode(adev, 0); + return r; +} - soft_reset = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); - soft_reset |= 1 << GRBM_SOFT_RESET__SOFT_RESET_SDMA0__SHIFT << inst_id; - - WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, soft_reset); - - udelay(50); - - soft_reset &= ~(1 << GRBM_SOFT_RESET__SOFT_RESET_SDMA0__SHIFT << inst_id); - WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, soft_reset); +static int sdma_v5_0_restore_queue(struct amdgpu_ring *ring) +{ + int r; + u32 freeze; + struct amdgpu_device *adev = ring->adev; + u32 inst_id = ring->me; + amdgpu_gfx_rlc_enter_safe_mode(adev, 0); /* unfreeze*/ freeze = RREG32(sdma_v5_0_get_reg_offset(adev, inst_id, mmSDMA0_FREEZE)); freeze = REG_SET_FIELD(freeze, SDMA0_FREEZE, FREEZE, 0); @@ -1572,7 +1582,6 @@ static int sdma_v5_0_reset_queue(struct amdgpu_ring *ring, unsigned int vmid) r = sdma_v5_0_gfx_resume_instance(adev, inst_id, true); -err0: amdgpu_gfx_rlc_exit_safe_mode(adev, 0); return r; } @@ -1919,6 +1928,8 @@ static const struct amdgpu_ring_funcs sdma_v5_0_ring_funcs = { .init_cond_exec = sdma_v5_0_ring_init_cond_exec, .preempt_ib = sdma_v5_0_ring_preempt_ib, .reset = sdma_v5_0_reset_queue, + .stop_queue = sdma_v5_0_stop_queue, + .start_queue = sdma_v5_0_restore_queue, }; static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev) -- 2.25.1