From: Sasha Levin <sashal@kernel.org>
To: patches@lists.linux.dev, stable@vger.kernel.org
Cc: Charlene Liu <Charlene.Liu@amd.com>,
Ovidiu Bunea <ovidiu.bunea@amd.com>,
Aurabindo Pillai <aurabindo.pillai@amd.com>,
Daniel Wheeler <daniel.wheeler@amd.com>,
Alex Deucher <alexander.deucher@amd.com>,
Sasha Levin <sashal@kernel.org>,
austin.zheng@amd.com, jun.lei@amd.com, harry.wentland@amd.com,
sunpeng.li@amd.com, christian.koenig@amd.com, airlied@gmail.com,
simona@ffwll.ch, amd-gfx@lists.freedesktop.org,
dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org
Subject: [PATCH AUTOSEL 6.14 040/102] drm/amd/display: fix zero value for APU watermark_c
Date: Sun, 1 Jun 2025 19:28:32 -0400 [thread overview]
Message-ID: <20250601232937.3510379-40-sashal@kernel.org> (raw)
In-Reply-To: <20250601232937.3510379-1-sashal@kernel.org>
From: Charlene Liu <Charlene.Liu@amd.com>
[ Upstream commit d5a7fdc88a2d64242d959942cbd0e1499ebb9806 ]
[why]
the guard of is_apu not in sync, caused no watermark_c output.
Reviewed-by: Ovidiu Bunea <ovidiu.bunea@amd.com>
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
**YES** This commit should be backported to stable kernel trees. Here's
my extensive analysis: ## Bug Analysis The commit fixes a critical bug
in AMD display driver's watermark handling for APU (Accelerated
Processing Unit) systems. The issue is in the
`dml2_validate_and_build_resource` function where watermark_c was being
incorrectly populated for APU systems. ## Problem Description **Before
the fix:** ```c memcpy(&context->bw_ctx.bw.dcn.watermarks.c,
&dml2->v20.g6_temp_read_watermark_set,
sizeof(context->bw_ctx.bw.dcn.watermarks.c)); ``` **After the fix:**
```c if (context->streams[0]->sink->link->dc->caps.is_apu)
dml2_extract_watermark_set(&context->bw_ctx.bw.dcn.watermarks.c,
&dml2->v20.dml_core_ctx); else
memcpy(&context->bw_ctx.bw.dcn.watermarks.c,
&dml2->v20.g6_temp_read_watermark_set,
sizeof(context->bw_ctx.bw.dcn.watermarks.c)); ``` ## Why This is a Good
Backport Candidate 1. **Clear Bug Fix**: The commit message explicitly
states "the guard of is_apu not in sync, caused no watermark_c output" -
this indicates a bug where APU systems were getting incorrect (likely
zero) watermark values. 2. **Consistent Pattern**: Looking at the same
file (line 546, 561, 569), there are already multiple `is_apu` checks
that differentiate behavior between APU and discrete GPU systems. The
original code at line 666 was inconsistent with this pattern. 3. **Small
and Contained**: The fix is minimal - just adding a conditional check
around an existing operation. It doesn't introduce new functionality or
architectural changes. 4. **Critical Subsystem**: Display watermarks are
critical for preventing display artifacts, screen corruption, underflow
issues, and power management problems. Incorrect watermarks can cause
visible display problems for users. 5. **APU-Specific Impact**: APUs
(integrated GPU+CPU) are very common in laptops and budget systems. A
watermark bug affecting these systems would impact a large user base. 6.
**Comparison with Similar Commits**: Looking at the similar commits
provided: - Commits #2 and #4 with "YES" status fix watermark values to
prevent "flickering and OTC underflow" - This commit follows the same
pattern of fixing watermark-related display issues ## Risk Assessment
**Low Risk:** - The change only affects APU systems (`is_apu` check) -
For non-APU systems, behavior remains exactly the same - The fix aligns
the watermark_c handling with how watermarks a, b, and d are already
handled - Uses existing, well-tested `dml2_extract_watermark_set()`
function instead of raw memcpy ## Context from Kernel Investigation The
git blame shows the original problematic code was introduced in commit
7966f319c66d9 (July 2023) when DML2 was first introduced. This suggests
the bug has existed since DML2 was added, affecting APU users for
potentially over a year. The fix ensures APU systems get proper
watermark calculations via `dml2_extract_watermark_set()` instead of
using potentially incorrect temporary values from
`g6_temp_read_watermark_set`. **Conclusion**: This is a clear, low-risk
bug fix that addresses display functionality issues on a common class of
hardware (APUs) and follows stable tree criteria perfectly.
drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c b/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c
index d0f9df2daeb41..0c535f9602da3 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c
@@ -663,7 +663,10 @@ static bool dml2_validate_and_build_resource(const struct dc *in_dc, struct dc_s
dml2_copy_clocks_to_dc_state(&out_clks, context);
dml2_extract_watermark_set(&context->bw_ctx.bw.dcn.watermarks.a, &dml2->v20.dml_core_ctx);
dml2_extract_watermark_set(&context->bw_ctx.bw.dcn.watermarks.b, &dml2->v20.dml_core_ctx);
- memcpy(&context->bw_ctx.bw.dcn.watermarks.c, &dml2->v20.g6_temp_read_watermark_set, sizeof(context->bw_ctx.bw.dcn.watermarks.c));
+ if (context->streams[0]->sink->link->dc->caps.is_apu)
+ dml2_extract_watermark_set(&context->bw_ctx.bw.dcn.watermarks.c, &dml2->v20.dml_core_ctx);
+ else
+ memcpy(&context->bw_ctx.bw.dcn.watermarks.c, &dml2->v20.g6_temp_read_watermark_set, sizeof(context->bw_ctx.bw.dcn.watermarks.c));
dml2_extract_watermark_set(&context->bw_ctx.bw.dcn.watermarks.d, &dml2->v20.dml_core_ctx);
dml2_extract_writeback_wm(context, &dml2->v20.dml_core_ctx);
//copy for deciding zstate use
--
2.39.5
next prev parent reply other threads:[~2025-06-01 23:31 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-01 23:27 [PATCH AUTOSEL 6.14 001/102] drm/amd/display: disable DPP RCG before DPP CLK enable Sasha Levin
2025-06-01 23:27 ` [PATCH AUTOSEL 6.14 003/102] drm/amdgpu/gfx6: fix CSIB handling Sasha Levin
2025-06-01 23:28 ` [PATCH AUTOSEL 6.14 008/102] drm/amdgpu: Fix API status offset for MES queue reset Sasha Levin
2025-06-01 23:28 ` [PATCH AUTOSEL 6.14 009/102] drm/amd/display: DCN32 null data check Sasha Levin
2025-06-01 23:28 ` [PATCH AUTOSEL 6.14 020/102] drm/amdkfd: Drop workaround for GC v9.4.3 revID 0 Sasha Levin
2025-06-01 23:28 ` [PATCH AUTOSEL 6.14 021/102] drm/amdgpu/gfx11: fix CSIB handling Sasha Levin
2025-06-01 23:28 ` [PATCH AUTOSEL 6.14 025/102] drm/amd/display: Avoid divide by zero by initializing dummy pitch to 1 Sasha Levin
2025-06-01 23:28 ` [PATCH AUTOSEL 6.14 029/102] drm/amd/display: Add NULL pointer checks in dm_force_atomic_commit() Sasha Levin
2025-06-01 23:28 ` [PATCH AUTOSEL 6.14 031/102] drm/amd/display: Skip to enable dsc if it has been off Sasha Levin
2025-06-01 23:28 ` [PATCH AUTOSEL 6.14 034/102] drm/amd/display: Do Not Consider DSC if Valid Config Not Found Sasha Levin
2025-06-01 23:28 ` [PATCH AUTOSEL 6.14 036/102] drm/amdgpu/gfx10: fix CSIB handling Sasha Levin
2025-06-01 23:28 ` Sasha Levin [this message]
2025-06-01 23:28 ` [PATCH AUTOSEL 6.14 042/102] drm/amdgpu/gfx7: " Sasha Levin
2025-06-01 23:28 ` [PATCH AUTOSEL 6.14 047/102] drm/amd/display: Correct SSC enable detection for DCN351 Sasha Levin
2025-06-01 23:28 ` [PATCH AUTOSEL 6.14 051/102] drm/amdgpu: fix MES GFX mask Sasha Levin
2025-06-01 23:28 ` [PATCH AUTOSEL 6.14 052/102] drm/amdgpu: Disallow partition query during reset Sasha Levin
2025-06-01 23:28 ` [PATCH AUTOSEL 6.14 055/102] drm/amdgpu/gfx8: fix CSIB handling Sasha Levin
2025-06-01 23:28 ` [PATCH AUTOSEL 6.14 056/102] drm/amd/display: disable EASF narrow filter sharpening Sasha Levin
2025-06-01 23:28 ` [PATCH AUTOSEL 6.14 057/102] drm/amdgpu/gfx9: fix CSIB handling Sasha Levin
2025-06-01 23:28 ` [PATCH AUTOSEL 6.14 058/102] drm/amd/display: Fix VUpdate offset calculations for dcn401 Sasha Levin
2025-06-01 23:28 ` [PATCH AUTOSEL 6.14 060/102] drm/amd/display: Correct prefetch calculation Sasha Levin
2025-06-01 23:28 ` [PATCH AUTOSEL 6.14 061/102] drm/amd/display: Restructure DMI quirks Sasha Levin
2025-06-01 23:28 ` [PATCH AUTOSEL 6.14 064/102] drm/amdkfd: Set SDMA_RLCx_IB_CNTL/SWITCH_INSIDE_IB Sasha Levin
2025-06-01 23:29 ` [PATCH AUTOSEL 6.14 070/102] drm/amdgpu: Add indirect L1_TLB_CNTL reg programming for VFs Sasha Levin
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