* [PATCH 0/2] Restore cached power limit and custom clocks
@ 2025-07-25 3:12 Mario Limonciello
2025-07-25 3:12 ` [PATCH 1/2] drm/amd: Restore cached power limit during resume Mario Limonciello
2025-07-25 3:12 ` [PATCH 2/2] drm/amd: Restore cached manual clock settings " Mario Limonciello
0 siblings, 2 replies; 4+ messages in thread
From: Mario Limonciello @ 2025-07-25 3:12 UTC (permalink / raw)
To: amd-gfx; +Cc: Mario Limonciello
From: Mario Limonciello <mario.limonciello@amd.com>
If userspace has programmed a custom power limit and/or custom clock
table the state will not be maintained across an S3 suspend cycle.
The values are already cached, so restore them in the resume sequence.
Mario Limonciello (2):
drm/amd: Restore cached power limit during resume
drm/amd: Restore cached manual clock settings during resume
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
--
2.43.0
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH 1/2] drm/amd: Restore cached power limit during resume
2025-07-25 3:12 [PATCH 0/2] Restore cached power limit and custom clocks Mario Limonciello
@ 2025-07-25 3:12 ` Mario Limonciello
2025-07-28 17:51 ` Alex Deucher
2025-07-25 3:12 ` [PATCH 2/2] drm/amd: Restore cached manual clock settings " Mario Limonciello
1 sibling, 1 reply; 4+ messages in thread
From: Mario Limonciello @ 2025-07-25 3:12 UTC (permalink / raw)
To: amd-gfx; +Cc: Mario Limonciello
From: Mario Limonciello <mario.limonciello@amd.com>
The power limit will be cached in smu->current_power_limit but
if the ASIC goes into S3 this value won't be restored.
Restore the value during SMU resume.
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index d79a1d94661a5..7537964c3c998 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -2175,6 +2175,12 @@ static int smu_resume(struct amdgpu_ip_block *ip_block)
adev->pm.dpm_enabled = true;
+ if (smu->current_power_limit) {
+ ret = smu_set_power_limit(smu, smu->current_power_limit);
+ if (ret && ret != -EOPNOTSUPP)
+ return ret;
+ }
+
dev_info(adev->dev, "SMU is resumed successfully!\n");
return 0;
--
2.43.0
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH 2/2] drm/amd: Restore cached manual clock settings during resume
2025-07-25 3:12 [PATCH 0/2] Restore cached power limit and custom clocks Mario Limonciello
2025-07-25 3:12 ` [PATCH 1/2] drm/amd: Restore cached power limit during resume Mario Limonciello
@ 2025-07-25 3:12 ` Mario Limonciello
1 sibling, 0 replies; 4+ messages in thread
From: Mario Limonciello @ 2025-07-25 3:12 UTC (permalink / raw)
To: amd-gfx; +Cc: Mario Limonciello
From: Mario Limonciello <mario.limonciello@amd.com>
If the SCLK limits have been set before S3 they will not
be restored. The limits are however cached in the driver and so
they can be restored by running a commit sequence during resume.
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 7537964c3c998..26b8e232f8582 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -76,6 +76,9 @@ static void smu_power_profile_mode_get(struct smu_context *smu,
enum PP_SMC_POWER_PROFILE profile_mode);
static void smu_power_profile_mode_put(struct smu_context *smu,
enum PP_SMC_POWER_PROFILE profile_mode);
+static int smu_od_edit_dpm_table(void *handle,
+ enum PP_OD_DPM_TABLE_COMMAND type,
+ long *input, uint32_t size);
static int smu_sys_get_pp_feature_mask(void *handle,
char *buf)
@@ -2144,6 +2147,7 @@ static int smu_resume(struct amdgpu_ip_block *ip_block)
int ret;
struct amdgpu_device *adev = ip_block->adev;
struct smu_context *smu = adev->powerplay.pp_handle;
+ struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
if (amdgpu_sriov_multi_vf_mode(adev))
return 0;
@@ -2181,6 +2185,12 @@ static int smu_resume(struct amdgpu_ip_block *ip_block)
return ret;
}
+ if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
+ ret = smu_od_edit_dpm_table(smu, PP_OD_COMMIT_DPM_TABLE, NULL, 0);
+ if (ret)
+ return ret;
+ }
+
dev_info(adev->dev, "SMU is resumed successfully!\n");
return 0;
--
2.43.0
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH 1/2] drm/amd: Restore cached power limit during resume
2025-07-25 3:12 ` [PATCH 1/2] drm/amd: Restore cached power limit during resume Mario Limonciello
@ 2025-07-28 17:51 ` Alex Deucher
0 siblings, 0 replies; 4+ messages in thread
From: Alex Deucher @ 2025-07-28 17:51 UTC (permalink / raw)
To: Mario Limonciello; +Cc: amd-gfx, Mario Limonciello
Series is:
Acked-by: Alex Deucher <alexander.deucher@amd.com>
On Thu, Jul 24, 2025 at 11:18 PM Mario Limonciello <superm1@kernel.org> wrote:
>
> From: Mario Limonciello <mario.limonciello@amd.com>
>
> The power limit will be cached in smu->current_power_limit but
> if the ASIC goes into S3 this value won't be restored.
>
> Restore the value during SMU resume.
>
> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
> ---
> drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> index d79a1d94661a5..7537964c3c998 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> @@ -2175,6 +2175,12 @@ static int smu_resume(struct amdgpu_ip_block *ip_block)
>
> adev->pm.dpm_enabled = true;
>
> + if (smu->current_power_limit) {
> + ret = smu_set_power_limit(smu, smu->current_power_limit);
> + if (ret && ret != -EOPNOTSUPP)
> + return ret;
> + }
> +
> dev_info(adev->dev, "SMU is resumed successfully!\n");
>
> return 0;
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2025-07-28 17:52 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
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2025-07-25 3:12 [PATCH 0/2] Restore cached power limit and custom clocks Mario Limonciello
2025-07-25 3:12 ` [PATCH 1/2] drm/amd: Restore cached power limit during resume Mario Limonciello
2025-07-28 17:51 ` Alex Deucher
2025-07-25 3:12 ` [PATCH 2/2] drm/amd: Restore cached manual clock settings " Mario Limonciello
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