* [PATCH 0/5] Expand kernel-doc with more generic details and info about ring buffers
@ 2025-08-16 15:31 Rodrigo Siqueira
2025-08-16 15:31 ` [PATCH 1/5] drm/amdgpu: Expand kernel-doc in amdgpu_ring Rodrigo Siqueira
` (4 more replies)
0 siblings, 5 replies; 12+ messages in thread
From: Rodrigo Siqueira @ 2025-08-16 15:31 UTC (permalink / raw)
To: Alex Deucher, Christian König, Timur Kristóf
Cc: amd-gfx, kernel-dev, Rodrigo Siqueira
Lately, I have been part of multiple discussions around GPU recovery and
other concepts associated with GFX/Compute. Most of the debate is spread
around GitLab issues, emails, and some meeting conversations. This
patchset aims to consolidate all that information into a single
kernel-doc, which can be collaboratively improved and shared with other
people.
In this series, you will find new amdgpu glossary entries, more details
about the IPs' interconnections, and a description of the ring buffer.
This series includes multiple SVG diagrams; for this reason, it might be
good to apply this series locally.
Finally, keep in mind that I tried to fill in some gaps between
information, and hopefully, my description matches the reality.
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Christian König <christian.koenig@amd.com>
Cc: Timur Kristóf <timur.kristof@gmail.com>
Thanks
Rodrigo Siqueira (5):
drm/amdgpu: Expand kernel-doc in amdgpu_ring
Documentation/gpu: Add new glossary entries from UMR
Documentation/gpu: Expand generic block information
Documentation/gpu: Add more information about GC
Documentation/gpu: Add documentation about ring buffer
.../gpu/amdgpu/amd_overview_block.svg | 674 +++++++
Documentation/gpu/amdgpu/amdgpu-glossary.rst | 24 +
Documentation/gpu/amdgpu/driver-core.rst | 25 +
.../gpu/amdgpu/enforce_isolation.svg | 707 +++++++
Documentation/gpu/amdgpu/gc/cu.svg | 437 +++++
Documentation/gpu/amdgpu/gc/index.rst | 28 +-
Documentation/gpu/amdgpu/gfx_pipeline_seq.svg | 413 +++++
Documentation/gpu/amdgpu/index.rst | 1 +
.../gpu/amdgpu/no_enforce_isolation.svg | 673 +++++++
Documentation/gpu/amdgpu/ring-buffer.rst | 94 +
Documentation/gpu/amdgpu/ring_buffers.svg | 1633 +++++++++++++++++
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 15 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 2 +
13 files changed, 4717 insertions(+), 9 deletions(-)
create mode 100644 Documentation/gpu/amdgpu/amd_overview_block.svg
create mode 100644 Documentation/gpu/amdgpu/enforce_isolation.svg
create mode 100644 Documentation/gpu/amdgpu/gc/cu.svg
create mode 100644 Documentation/gpu/amdgpu/gfx_pipeline_seq.svg
create mode 100644 Documentation/gpu/amdgpu/no_enforce_isolation.svg
create mode 100644 Documentation/gpu/amdgpu/ring-buffer.rst
create mode 100644 Documentation/gpu/amdgpu/ring_buffers.svg
--
2.47.2
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 1/5] drm/amdgpu: Expand kernel-doc in amdgpu_ring
2025-08-16 15:31 [PATCH 0/5] Expand kernel-doc with more generic details and info about ring buffers Rodrigo Siqueira
@ 2025-08-16 15:31 ` Rodrigo Siqueira
2025-08-18 12:30 ` Christian König
2025-08-16 15:31 ` [PATCH 2/5] Documentation/gpu: Add new glossary entries from UMR Rodrigo Siqueira
` (3 subsequent siblings)
4 siblings, 1 reply; 12+ messages in thread
From: Rodrigo Siqueira @ 2025-08-16 15:31 UTC (permalink / raw)
To: Alex Deucher, Christian König, Timur Kristóf
Cc: amd-gfx, kernel-dev, Rodrigo Siqueira
Expand the kernel-doc about amdgpu_ring and add some tiny improvements.
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Christian König <christian.koenig@amd.com>
Cc: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 15 ++++++++++++---
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 2 ++
2 files changed, 14 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
index 6379bb25bf5c..78fd324c84e9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
@@ -75,8 +75,16 @@ unsigned int amdgpu_ring_max_ibs(enum amdgpu_ring_type type)
* @ring: amdgpu_ring structure holding ring information
* @ndw: number of dwords to allocate in the ring buffer
*
- * Allocate @ndw dwords in the ring buffer (all asics).
- * Returns 0 on success, error on failure.
+ * Allocate @ndw dwords in the ring buffer (it works in all ASICs). When
+ * inspecting the code, you may encounter places where this function is called
+ * amdgpu_ring_alloc(ring, X + Y + Z) where X, Y, and Z are integer numbers.
+ * This is a way to show how many dwords operations will be inserted in the
+ * ring. For example, if gfx_v9_0_wait_reg_mem(), amdgpu_ring_emit_reg_wait(),
+ * amdgpu_ring_emit_wreg(), and amdgpu_ring_emit_fence() will be called, before
+ * that you will see amdgpu_ring_alloc(ring, 7 + 7 + 5 + 8).
+ *
+ * Returns:
+ * 0 on success, error on failure.
*/
int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned int ndw)
{
@@ -122,7 +130,8 @@ static void amdgpu_ring_alloc_reemit(struct amdgpu_ring *ring, unsigned int ndw)
ring->funcs->begin_use(ring);
}
-/** amdgpu_ring_insert_nop - insert NOP packets
+/**
+ * amdgpu_ring_insert_nop - insert NOP packets
*
* @ring: amdgpu_ring structure holding ring information
* @count: the number of NOP packets to insert
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index 7670f5d82b9e..d27dbb3c109f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -62,6 +62,8 @@ enum amdgpu_ring_priority_level {
#define AMDGPU_FENCE_FLAG_64BIT (1 << 0)
#define AMDGPU_FENCE_FLAG_INT (1 << 1)
#define AMDGPU_FENCE_FLAG_TC_WB_ONLY (1 << 2)
+
+/* Ensure the execution in case of preemption or reset */
#define AMDGPU_FENCE_FLAG_EXEC (1 << 3)
#define to_amdgpu_ring(s) container_of((s), struct amdgpu_ring, sched)
--
2.47.2
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 2/5] Documentation/gpu: Add new glossary entries from UMR
2025-08-16 15:31 [PATCH 0/5] Expand kernel-doc with more generic details and info about ring buffers Rodrigo Siqueira
2025-08-16 15:31 ` [PATCH 1/5] drm/amdgpu: Expand kernel-doc in amdgpu_ring Rodrigo Siqueira
@ 2025-08-16 15:31 ` Rodrigo Siqueira
2025-08-19 18:50 ` Timur Kristóf
2025-08-16 15:31 ` [PATCH 3/5] Documentation/gpu: Expand generic block information Rodrigo Siqueira
` (2 subsequent siblings)
4 siblings, 1 reply; 12+ messages in thread
From: Rodrigo Siqueira @ 2025-08-16 15:31 UTC (permalink / raw)
To: Alex Deucher, Christian König, Timur Kristóf
Cc: amd-gfx, kernel-dev, Rodrigo Siqueira
When using UMR, a dashboard is available that displays the CPC, CPF,
CPG, TCP, and UTCL utilization. This commit introduces the meanings of
those acronyms (and others) to the glossary to improve the comprehension
of the UMR dashboard.
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Christian König <christian.koenig@amd.com>
Cc: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com>
---
Documentation/gpu/amdgpu/amdgpu-glossary.rst | 21 ++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/Documentation/gpu/amdgpu/amdgpu-glossary.rst b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
index 30812d9d53c6..eb72e6f6d4f1 100644
--- a/Documentation/gpu/amdgpu/amdgpu-glossary.rst
+++ b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
@@ -30,6 +30,15 @@ we have a dedicated glossary for Display Core at
CP
Command Processor
+ CPC
+ Command Processor Compute
+
+ CPF
+ Command Processor Fetch
+
+ CPG
+ Command Processor Graphics
+
CPLIB
Content Protection Library
@@ -78,6 +87,9 @@ we have a dedicated glossary for Display Core at
GMC
Graphic Memory Controller
+ GPR
+ General Purpose Register
+
GPUVM
GPU Virtual Memory. This is the GPU's MMU. The GPU supports multiple
virtual address spaces that can be in flight at any given time. These
@@ -92,6 +104,9 @@ we have a dedicated glossary for Display Core at
table for use by the kernel driver or into per process GPUVM page tables
for application usage.
+ GWS
+ Global Wave Syncs
+
IH
Interrupt Handler
@@ -206,12 +221,18 @@ we have a dedicated glossary for Display Core at
TC
Texture Cache
+ TCP (AMDGPU)
+ Texture Cache Processing
+
TOC
Table of Contents
UMSCH
User Mode Scheduler
+ UTCL
+ Universal Texture Cache Line
+
UVD
Unified Video Decoder
--
2.47.2
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 3/5] Documentation/gpu: Expand generic block information
2025-08-16 15:31 [PATCH 0/5] Expand kernel-doc with more generic details and info about ring buffers Rodrigo Siqueira
2025-08-16 15:31 ` [PATCH 1/5] drm/amdgpu: Expand kernel-doc in amdgpu_ring Rodrigo Siqueira
2025-08-16 15:31 ` [PATCH 2/5] Documentation/gpu: Add new glossary entries from UMR Rodrigo Siqueira
@ 2025-08-16 15:31 ` Rodrigo Siqueira
2025-08-16 15:31 ` [PATCH 4/5] Documentation/gpu: Add more information about GC Rodrigo Siqueira
2025-08-16 15:31 ` [PATCH 5/5] Documentation/gpu: Add documentation about ring buffer Rodrigo Siqueira
4 siblings, 0 replies; 12+ messages in thread
From: Rodrigo Siqueira @ 2025-08-16 15:31 UTC (permalink / raw)
To: Alex Deucher, Christian König, Timur Kristóf
Cc: amd-gfx, kernel-dev, Rodrigo Siqueira
This commit expands the overall explanation about AMD GPU IPs by adding
more details about their interconnection. Note that this commit includes
a diagram that provides additional information.
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Christian König <christian.koenig@amd.com>
Cc: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com>
---
.../gpu/amdgpu/amd_overview_block.svg | 674 ++++++++++++++++++
Documentation/gpu/amdgpu/amdgpu-glossary.rst | 3 +
Documentation/gpu/amdgpu/driver-core.rst | 25 +
3 files changed, 702 insertions(+)
create mode 100644 Documentation/gpu/amdgpu/amd_overview_block.svg
diff --git a/Documentation/gpu/amdgpu/amd_overview_block.svg b/Documentation/gpu/amdgpu/amd_overview_block.svg
new file mode 100644
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diff --git a/Documentation/gpu/amdgpu/amdgpu-glossary.rst b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
index eb72e6f6d4f1..a3f9565d655b 100644
--- a/Documentation/gpu/amdgpu/amdgpu-glossary.rst
+++ b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
@@ -227,6 +227,9 @@ we have a dedicated glossary for Display Core at
TOC
Table of Contents
+ UMC
+ Unified Memory Controller
+
UMSCH
User Mode Scheduler
diff --git a/Documentation/gpu/amdgpu/driver-core.rst b/Documentation/gpu/amdgpu/driver-core.rst
index 81256318e93c..f47199c04d8f 100644
--- a/Documentation/gpu/amdgpu/driver-core.rst
+++ b/Documentation/gpu/amdgpu/driver-core.rst
@@ -77,6 +77,31 @@ VCN (Video Core Next)
decode. It's exposed to userspace for user mode drivers (VA-API,
OpenMAX, etc.)
+It is important to note that these blocks can interact with each other. The
+picture below illustrates some of the components and their interconnection:
+
+.. kernel-figure:: amd_overview_block.svg
+
+In the diagram, memory-related blocks are represented by a green color. Notice
+that specific IPs have a green block that represents a small hardware block
+named 'hub', which is responsible for interfacing with memory (pre-vega devices
+have a dedicated block for that, named GMC). In the driver code, you can
+identify this component by looking for the suffix hub, for example: gfxhub,
+dchub, mmhub, vmhub, etc. All memory hubs are connected in the UMC, which in
+turn is connected to memory blocks.
+
+There is some level of protection for certain elements in memory, and the PSP
+plays an essential role in this area. For example, when a specific firmware is
+loaded into the memory, PSP takes an action to ensure that the firmware has a
+valid signature. Another use of PSP is to support the TA (e.g., HDCP) and
+encrypted memory via TMZ.
+
+Another IP that deserves attention is the SMU, as it is connected to all the
+other IPs. SMU will help put the GPU in optimal utilization by taking into
+account performance and power consumption. SMU helps other blocks to set up a
+proper clock configuration. Another feature of SMU is the support for resetting
+every component.
+
.. _pipes-and-queues-description:
GFX, Compute, and SDMA Overall Behavior
--
2.47.2
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 4/5] Documentation/gpu: Add more information about GC
2025-08-16 15:31 [PATCH 0/5] Expand kernel-doc with more generic details and info about ring buffers Rodrigo Siqueira
` (2 preceding siblings ...)
2025-08-16 15:31 ` [PATCH 3/5] Documentation/gpu: Expand generic block information Rodrigo Siqueira
@ 2025-08-16 15:31 ` Rodrigo Siqueira
2025-08-16 15:31 ` [PATCH 5/5] Documentation/gpu: Add documentation about ring buffer Rodrigo Siqueira
4 siblings, 0 replies; 12+ messages in thread
From: Rodrigo Siqueira @ 2025-08-16 15:31 UTC (permalink / raw)
To: Alex Deucher, Christian König, Timur Kristóf
Cc: amd-gfx, kernel-dev, Rodrigo Siqueira
This commit introduces a diagram and a set of information that details
the different sets of schedulers available in the SE.
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Christian König <christian.koenig@amd.com>
Cc: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com>
---
Documentation/gpu/amdgpu/gc/cu.svg | 437 ++++++++++++++++++++++++++
Documentation/gpu/amdgpu/gc/index.rst | 28 +-
2 files changed, 459 insertions(+), 6 deletions(-)
create mode 100644 Documentation/gpu/amdgpu/gc/cu.svg
diff --git a/Documentation/gpu/amdgpu/gc/cu.svg b/Documentation/gpu/amdgpu/gc/cu.svg
new file mode 100644
index 000000000000..10bdb3e24b65
--- /dev/null
+++ b/Documentation/gpu/amdgpu/gc/cu.svg
@@ -0,0 +1,437 @@
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diff --git a/Documentation/gpu/amdgpu/gc/index.rst b/Documentation/gpu/amdgpu/gc/index.rst
index ff6e9ef5cbee..7110b4966729 100644
--- a/Documentation/gpu/amdgpu/gc/index.rst
+++ b/Documentation/gpu/amdgpu/gc/index.rst
@@ -10,16 +10,32 @@ producer-consumer problem, where the CPU fills out a buffer with operations
the buffer are called Command Packets, which can be summarized as a compressed
way of transmitting command information to the graphics controller.
+In the diagram below, you can see an overview of the GC, along with additional
+information about the Shader Engine (SE).
+
+.. kernel-figure:: cu.svg
+
+First of all, note that the GC can have multiple SEs, depending on the specific
+GPU/APU, and each SE has multiple Compute Units (CU). From the diagram, you can
+see that CUs have a block named Schedulers. The reason the name is in plural is
+because this block is a combination of different micro-schedules: CP, CPF, CPC,
+and CPG.
+
The component that acts as the front end between the CPU and the GPU is called
-the Command Processor (CP). This component is responsible for providing greater
+CP (Command Processor). This component is responsible for providing greater
flexibility to the GC since CP makes it possible to program various aspects of
the GPU pipeline. CP also coordinates the communication between the CPU and GPU
via a mechanism named **Ring Buffers**, where the CPU appends information to
-the buffer while the GPU removes operations. It is relevant to highlight that a
-CPU can add a pointer to the Ring Buffer that points to another region of
-memory outside the Ring Buffer, and CP can handle it; this mechanism is called
-**Indirect Buffer (IB)**. CP receives and parses the Command Streams (CS), and
-writes the operations to the correct hardware blocks.
+the buffer while the GPU removes operations. Finally, CP is also responsible
+for handling Indirect Buffers (IB).
+
+After CP completes the first set of processing, which includes separate command
+packets specific to GFX and Compute, other blocks step in. To handle commands
+for the compute block, CPC (Command Processor Command) takes over, and for
+handling Graphics operations, the CPG (Command Processor Graphics) takes
+action. Another essential block to ensure the optimal utilization of CPC and
+CPG is the CPF (Command Processor Fetcher), which helps these blocks to be
+constantly fed.
Graphics (GFX) and Compute Microcontrollers
-------------------------------------------
--
2.47.2
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 5/5] Documentation/gpu: Add documentation about ring buffer
2025-08-16 15:31 [PATCH 0/5] Expand kernel-doc with more generic details and info about ring buffers Rodrigo Siqueira
` (3 preceding siblings ...)
2025-08-16 15:31 ` [PATCH 4/5] Documentation/gpu: Add more information about GC Rodrigo Siqueira
@ 2025-08-16 15:31 ` Rodrigo Siqueira
4 siblings, 0 replies; 12+ messages in thread
From: Rodrigo Siqueira @ 2025-08-16 15:31 UTC (permalink / raw)
To: Alex Deucher, Christian König, Timur Kristóf
Cc: amd-gfx, kernel-dev, Rodrigo Siqueira
AMDGPU heavily relies on ring buffers to manage its components; as a
result, it has an elaborate mechanism of operation with multiple details
around it. This commit introduces new documentation on ring buffers,
detailing their management and expanding the explanation of Enforce
isolation. Finally, this commit also adds the documentation available in
the amdgpu_ring.c file to it.
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Christian König <christian.koenig@amd.com>
Cc: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com>
---
.../gpu/amdgpu/enforce_isolation.svg | 707 +++++++
Documentation/gpu/amdgpu/gfx_pipeline_seq.svg | 413 +++++
Documentation/gpu/amdgpu/index.rst | 1 +
.../gpu/amdgpu/no_enforce_isolation.svg | 673 +++++++
Documentation/gpu/amdgpu/ring-buffer.rst | 94 +
Documentation/gpu/amdgpu/ring_buffers.svg | 1633 +++++++++++++++++
6 files changed, 3521 insertions(+)
create mode 100644 Documentation/gpu/amdgpu/enforce_isolation.svg
create mode 100644 Documentation/gpu/amdgpu/gfx_pipeline_seq.svg
create mode 100644 Documentation/gpu/amdgpu/no_enforce_isolation.svg
create mode 100644 Documentation/gpu/amdgpu/ring-buffer.rst
create mode 100644 Documentation/gpu/amdgpu/ring_buffers.svg
diff --git a/Documentation/gpu/amdgpu/enforce_isolation.svg b/Documentation/gpu/amdgpu/enforce_isolation.svg
new file mode 100644
index 000000000000..b224615e1611
--- /dev/null
+++ b/Documentation/gpu/amdgpu/enforce_isolation.svg
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diff --git a/Documentation/gpu/amdgpu/index.rst b/Documentation/gpu/amdgpu/index.rst
index bb2894b5edaf..1f0e8a38c625 100644
--- a/Documentation/gpu/amdgpu/index.rst
+++ b/Documentation/gpu/amdgpu/index.rst
@@ -8,6 +8,7 @@ Next (GCN), Radeon DNA (RDNA), and Compute DNA (CDNA) architectures.
.. toctree::
driver-core
+ ring-buffer
amd-hardware-list-info
module-parameters
gc/index
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diff --git a/Documentation/gpu/amdgpu/ring-buffer.rst b/Documentation/gpu/amdgpu/ring-buffer.rst
new file mode 100644
index 000000000000..40c189c9dab4
--- /dev/null
+++ b/Documentation/gpu/amdgpu/ring-buffer.rst
@@ -0,0 +1,94 @@
+=============
+ Ring Buffer
+=============
+
+To handle communication between user space and kernel space, amdgpu adopts a
+strategy based on a ring buffer, which is used by GFX, Compute, SDMA, UVD, VCE,
+VCN, VPE, KIQ, MES, UMSCH, and CPER. See the figure below that illustrates how
+this communication works:
+
+.. kernel-figure:: ring_buffers.svg
+
+Ring buffers in the amdgpu work as a producer-consumer problem, where userspace
+acts as the producer, constantly filling the ring buffer with GPU commands to
+be executed. Meanwhile, the GPU retrieves the information from the ring, parses
+it, and distributes the specific set of instructions between the different
+amdgpu blocks. Notice from the diagram that the ring has a Read Pointer (rptr)
+that indicates where the GPU is currently reading, and there is a Write Pointer
+(wptr) that indicates where the host has written the message. Note that every
+time something is written to the ring, the wptr is incremented. Meanwhile, the
+GPU constantly updates the rptr pointer, chasing the wptr until both pointers
+are equal. The user space or the driver can utilize the rptr pointer to roughly
+estimate how many instructions are still pending completion (keep in mind that
+rptr might not be precise).
+
+Usually, ring buffers in the driver have a limited size (search for occurrences
+of `amdgpu_ring_init()`). One of the reasons for the small ring buffer size is
+that CP (Command Processor) is capable of following addresses inserted into the
+ring; this is illustrated in the image by the reference to the IB (Indirect
+Buffer). The IB gives userspace the possibility to have an area in memory that
+CP can read and feed the hardware with extra instructions.
+
+Enforce Isolation
+=================
+
+Before examining the Enforce Isolation mechanism in the ring buffer context, it
+is important to discuss two concepts: where the ring buffer is located and how
+instructions from the ring buffer are processed in the graphics pipeline.
+
+All ASICs pre-GFX11 use what is called a kernel queue, which means the ring is
+allocated in kernel space and has some restrictions, such as not being able to
+map and unmap queues after initialization. GFX12 and newer support kernel
+queues, but also provide a new mechanism named user queues, where the queue is
+moved to the user space and can be mapped and unmapped. In practical terms, the
+kernel queue approach inserts all GPU commands created by userspace into the
+same set of rings, albeit in a mixed manner. See the picture below illustrating
+this scenario:
+
+.. kernel-figure:: no_enforce_isolation.svg
+
+Note from the diagram that there is no guarantee of order or a clear separation
+between instructions, which is not a problem most of the time, and this is also
+good for performance. In terms of executing those instructions in the GFX, it
+must follow a pipeline that usually follows the following sequence: Shader
+Export (SX), Geometry Engine (GE), Shader Process or Input (SPI), Scan
+Converter (SC), Primitive Assembler (PA), and cache manipulation (this may
+change between ASICs). Another common way to describe the pipeline is to use
+Pixel Shader (PS), raster, and Vertex Shader (VS) to symbolize the two shader
+stages. The diagram below illustrates the sequence described in the paragraph.
+
+.. kernel-figure:: gfx_pipeline_seq.svg
+
+The use of the kernel queue is the default behaviour in amdgpu pre-GFX11 and in
+many cases in newer ASICs. Although this solution is considered stable and
+performs well, it also creates some intricate issues when something goes wrong.
+The problem with this solution is that pinpointing which job caused an issue
+can be challenging in some situations, which can complicate the debugging in
+circumstances where the GPU recovery was triggered. For instance, if Job A
+causes a hang issue, Job B's instruction might already be executing, and we
+could incorrectly identify Job B as the problematic one. To mitigate this
+problem, it was introduced the concept of Enforce Isolation that can be seen in
+the below picture:
+
+.. kernel-figure:: enforce_isolation.svg
+
+As shown in the diagram, enforcing isolation introduces a level of ordering
+between submissions, since the access to GFX/Compute is serialized. Notice that
+this approach has a minimal performance impact, as it only allows one job to
+submit commands at a time. However, this is not a notable problem, and the
+benefit of better pinpointing the job that caused a problem outweighs the
+performance impact. Although enforcing isolation improves the situation, it
+does not fully resolve the issue of pinpointing bad jobs, as we can still
+encounter scenarios where Job A hangs while Job B is running, leading to the
+wrong blame of Job B. To avoid this issue, an additional element is introduced
+to enforce isolation, as represented by the circles in the diagram. Every
+circle is a wait for cache flushing, which ensures that when the next job
+starts, it starts in a clean state, and if some issues happen, we can point to
+the bad process more precisely.
+
+Ring Operations
+===============
+
+.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
+ :internal:
+
diff --git a/Documentation/gpu/amdgpu/ring_buffers.svg b/Documentation/gpu/amdgpu/ring_buffers.svg
new file mode 100644
index 000000000000..7a6fcb19e151
--- /dev/null
+++ b/Documentation/gpu/amdgpu/ring_buffers.svg
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--
2.47.2
^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH 1/5] drm/amdgpu: Expand kernel-doc in amdgpu_ring
2025-08-16 15:31 ` [PATCH 1/5] drm/amdgpu: Expand kernel-doc in amdgpu_ring Rodrigo Siqueira
@ 2025-08-18 12:30 ` Christian König
2025-08-20 22:43 ` Rodrigo Siqueira
0 siblings, 1 reply; 12+ messages in thread
From: Christian König @ 2025-08-18 12:30 UTC (permalink / raw)
To: Rodrigo Siqueira, Alex Deucher, Timur Kristóf; +Cc: amd-gfx, kernel-dev
On 16.08.25 17:31, Rodrigo Siqueira wrote:
> Expand the kernel-doc about amdgpu_ring and add some tiny improvements.
>
> Cc: Alex Deucher <alexander.deucher@amd.com>
> Cc: Christian König <christian.koenig@amd.com>
> Cc: Timur Kristóf <timur.kristof@gmail.com>
> Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 15 ++++++++++++---
> drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 2 ++
> 2 files changed, 14 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
> index 6379bb25bf5c..78fd324c84e9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
> @@ -75,8 +75,16 @@ unsigned int amdgpu_ring_max_ibs(enum amdgpu_ring_type type)
> * @ring: amdgpu_ring structure holding ring information
> * @ndw: number of dwords to allocate in the ring buffer
> *
> - * Allocate @ndw dwords in the ring buffer (all asics).
> - * Returns 0 on success, error on failure.
> + * Allocate @ndw dwords in the ring buffer (it works in all ASICs). When
> + * inspecting the code, you may encounter places where this function is called
> + * amdgpu_ring_alloc(ring, X + Y + Z) where X, Y, and Z are integer numbers.
> + * This is a way to show how many dwords operations will be inserted in the
> + * ring. For example, if gfx_v9_0_wait_reg_mem(), amdgpu_ring_emit_reg_wait(),
> + * amdgpu_ring_emit_wreg(), and amdgpu_ring_emit_fence() will be called, before
> + * that you will see amdgpu_ring_alloc(ring, 7 + 7 + 5 + 8).
Well the rest of the patch is certainly useful, but that here made me chuckle. Isn't that obvious?
> + *
> + * Returns:
> + * 0 on success, error on failure.
We should probably adjust the return value of the function from -ENOMEM to -EINVAL when the number of the requested DW exceeds the maximum and document that here.
Apart from that looks good to me.
Christian.
> */
> int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned int ndw)
> {
> @@ -122,7 +130,8 @@ static void amdgpu_ring_alloc_reemit(struct amdgpu_ring *ring, unsigned int ndw)
> ring->funcs->begin_use(ring);
> }
>
> -/** amdgpu_ring_insert_nop - insert NOP packets
> +/**
> + * amdgpu_ring_insert_nop - insert NOP packets
> *
> * @ring: amdgpu_ring structure holding ring information
> * @count: the number of NOP packets to insert
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> index 7670f5d82b9e..d27dbb3c109f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> @@ -62,6 +62,8 @@ enum amdgpu_ring_priority_level {
> #define AMDGPU_FENCE_FLAG_64BIT (1 << 0)
> #define AMDGPU_FENCE_FLAG_INT (1 << 1)
> #define AMDGPU_FENCE_FLAG_TC_WB_ONLY (1 << 2)
> +
> +/* Ensure the execution in case of preemption or reset */
> #define AMDGPU_FENCE_FLAG_EXEC (1 << 3)
>
> #define to_amdgpu_ring(s) container_of((s), struct amdgpu_ring, sched)
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 2/5] Documentation/gpu: Add new glossary entries from UMR
2025-08-16 15:31 ` [PATCH 2/5] Documentation/gpu: Add new glossary entries from UMR Rodrigo Siqueira
@ 2025-08-19 18:50 ` Timur Kristóf
2025-08-19 20:14 ` Alex Deucher
0 siblings, 1 reply; 12+ messages in thread
From: Timur Kristóf @ 2025-08-19 18:50 UTC (permalink / raw)
To: Rodrigo Siqueira, Alex Deucher, Christian König; +Cc: amd-gfx, kernel-dev
Hi,
On Sat, 2025-08-16 at 09:31 -0600, Rodrigo Siqueira wrote:
> When using UMR, a dashboard is available that displays the CPC, CPF,
> CPG, TCP, and UTCL utilization. This commit introduces the meanings
> of
> those acronyms (and others) to the glossary to improve the
> comprehension
> of the UMR dashboard.
>
> Cc: Alex Deucher <alexander.deucher@amd.com>
> Cc: Christian König <christian.koenig@amd.com>
> Cc: Timur Kristóf <timur.kristof@gmail.com>
> Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com>
> ---
> Documentation/gpu/amdgpu/amdgpu-glossary.rst | 21
> ++++++++++++++++++++
> 1 file changed, 21 insertions(+)
>
> diff --git a/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> index 30812d9d53c6..eb72e6f6d4f1 100644
> --- a/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> +++ b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> @@ -30,6 +30,15 @@ we have a dedicated glossary for Display Core at
> CP
> Command Processor
>
> + CPC
> + Command Processor Compute
> +
> + CPF
> + Command Processor Fetch
> +
> + CPG
> + Command Processor Graphics
> +
I would apprectiate a few more details here to connect these to other
glossary items. Here are a few questions:
- Is CPC the same as MEC?
- Is CPF the same as PFP?
- Is CPG the same as ME?
> CPLIB
> Content Protection Library
>
> @@ -78,6 +87,9 @@ we have a dedicated glossary for Display Core at
> GMC
> Graphic Memory Controller
>
> + GPR
> + General Purpose Register
> +
Does this refer to registers in shaders or registers in the various IP
blocks? If this is about shaders, it would be useful to mention that in
the context of shaders, a GPR is either SGPR or VGPR. (Those two are
already in the glossary.)
> GPUVM
> GPU Virtual Memory. This is the GPU's MMU. The GPU supports
> multiple
> virtual address spaces that can be in flight at any given
> time. These
> @@ -92,6 +104,9 @@ we have a dedicated glossary for Display Core at
> table for use by the kernel driver or into per process GPUVM
> page tables
> for application usage.
>
> + GWS
> + Global Wave Syncs
> +
> IH
> Interrupt Handler
>
> @@ -206,12 +221,18 @@ we have a dedicated glossary for Display Core
> at
> TC
> Texture Cache
>
> + TCP (AMDGPU)
> + Texture Cache Processing
> +
> TOC
> Table of Contents
>
> UMSCH
> User Mode Scheduler
>
> + UTCL
> + Universal Texture Cache Line
> +
> UVD
> Unified Video Decoder
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 2/5] Documentation/gpu: Add new glossary entries from UMR
2025-08-19 18:50 ` Timur Kristóf
@ 2025-08-19 20:14 ` Alex Deucher
2025-08-20 14:59 ` Timur Kristóf
0 siblings, 1 reply; 12+ messages in thread
From: Alex Deucher @ 2025-08-19 20:14 UTC (permalink / raw)
To: Timur Kristóf
Cc: Rodrigo Siqueira, Alex Deucher, Christian König, amd-gfx,
kernel-dev
On Tue, Aug 19, 2025 at 3:28 PM Timur Kristóf <timur.kristof@gmail.com> wrote:
>
> Hi,
>
> On Sat, 2025-08-16 at 09:31 -0600, Rodrigo Siqueira wrote:
> > When using UMR, a dashboard is available that displays the CPC, CPF,
> > CPG, TCP, and UTCL utilization. This commit introduces the meanings
> > of
> > those acronyms (and others) to the glossary to improve the
> > comprehension
> > of the UMR dashboard.
> >
> > Cc: Alex Deucher <alexander.deucher@amd.com>
> > Cc: Christian König <christian.koenig@amd.com>
> > Cc: Timur Kristóf <timur.kristof@gmail.com>
> > Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com>
> > ---
> > Documentation/gpu/amdgpu/amdgpu-glossary.rst | 21
> > ++++++++++++++++++++
> > 1 file changed, 21 insertions(+)
> >
> > diff --git a/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> > b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> > index 30812d9d53c6..eb72e6f6d4f1 100644
> > --- a/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> > +++ b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> > @@ -30,6 +30,15 @@ we have a dedicated glossary for Display Core at
> > CP
> > Command Processor
> >
> > + CPC
> > + Command Processor Compute
> > +
> > + CPF
> > + Command Processor Fetch
> > +
> > + CPG
> > + Command Processor Graphics
> > +
>
> I would apprectiate a few more details here to connect these to other
> glossary items. Here are a few questions:
>
> - Is CPC the same as MEC?
> - Is CPF the same as PFP?
> - Is CPG the same as ME?
CPC, CPF, and CPG are hardware blocks, MEC/PFP/ME are
microcontrollers. CPG contains the PFP and ME (and CE on chips which
support it). CPC contains MEC. CPF is another hardware block which
provides services to CPG and CPC.
Alex
>
> > CPLIB
> > Content Protection Library
> >
> > @@ -78,6 +87,9 @@ we have a dedicated glossary for Display Core at
> > GMC
> > Graphic Memory Controller
> >
> > + GPR
> > + General Purpose Register
> > +
>
> Does this refer to registers in shaders or registers in the various IP
> blocks? If this is about shaders, it would be useful to mention that in
> the context of shaders, a GPR is either SGPR or VGPR. (Those two are
> already in the glossary.)
>
> > GPUVM
> > GPU Virtual Memory. This is the GPU's MMU. The GPU supports
> > multiple
> > virtual address spaces that can be in flight at any given
> > time. These
> > @@ -92,6 +104,9 @@ we have a dedicated glossary for Display Core at
> > table for use by the kernel driver or into per process GPUVM
> > page tables
> > for application usage.
> >
> > + GWS
> > + Global Wave Syncs
> > +
> > IH
> > Interrupt Handler
> >
> > @@ -206,12 +221,18 @@ we have a dedicated glossary for Display Core
> > at
> > TC
> > Texture Cache
> >
> > + TCP (AMDGPU)
> > + Texture Cache Processing
> > +
> > TOC
> > Table of Contents
> >
> > UMSCH
> > User Mode Scheduler
> >
> > + UTCL
> > + Universal Texture Cache Line
> > +
> > UVD
> > Unified Video Decoder
> >
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 2/5] Documentation/gpu: Add new glossary entries from UMR
2025-08-19 20:14 ` Alex Deucher
@ 2025-08-20 14:59 ` Timur Kristóf
2025-08-20 22:25 ` Rodrigo Siqueira
0 siblings, 1 reply; 12+ messages in thread
From: Timur Kristóf @ 2025-08-20 14:59 UTC (permalink / raw)
To: Alex Deucher
Cc: Rodrigo Siqueira, Alex Deucher, Christian König, amd-gfx,
kernel-dev
On Tue, 2025-08-19 at 16:14 -0400, Alex Deucher wrote:
> On Tue, Aug 19, 2025 at 3:28 PM Timur Kristóf
> <timur.kristof@gmail.com> wrote:
> >
> > Hi,
> >
> > On Sat, 2025-08-16 at 09:31 -0600, Rodrigo Siqueira wrote:
> > > When using UMR, a dashboard is available that displays the CPC,
> > > CPF,
> > > CPG, TCP, and UTCL utilization. This commit introduces the
> > > meanings
> > > of
> > > those acronyms (and others) to the glossary to improve the
> > > comprehension
> > > of the UMR dashboard.
> > >
> > > Cc: Alex Deucher <alexander.deucher@amd.com>
> > > Cc: Christian König <christian.koenig@amd.com>
> > > Cc: Timur Kristóf <timur.kristof@gmail.com>
> > > Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com>
> > > ---
> > > Documentation/gpu/amdgpu/amdgpu-glossary.rst | 21
> > > ++++++++++++++++++++
> > > 1 file changed, 21 insertions(+)
> > >
> > > diff --git a/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> > > b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> > > index 30812d9d53c6..eb72e6f6d4f1 100644
> > > --- a/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> > > +++ b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> > > @@ -30,6 +30,15 @@ we have a dedicated glossary for Display Core
> > > at
> > > CP
> > > Command Processor
> > >
> > > + CPC
> > > + Command Processor Compute
> > > +
> > > + CPF
> > > + Command Processor Fetch
> > > +
> > > + CPG
> > > + Command Processor Graphics
> > > +
> >
> > I would apprectiate a few more details here to connect these to
> > other
> > glossary items. Here are a few questions:
> >
> > - Is CPC the same as MEC?
> > - Is CPF the same as PFP?
> > - Is CPG the same as ME?
>
> CPC, CPF, and CPG are hardware blocks, MEC/PFP/ME are
> microcontrollers. CPG contains the PFP and ME (and CE on chips which
> support it). CPC contains MEC. CPF is another hardware block which
> provides services to CPG and CPC.
Thanks for the clarification.
Siquiera - could we add that also to the glossary?
Thanks,
Timur
>
>
> >
> > > CPLIB
> > > Content Protection Library
> > >
> > > @@ -78,6 +87,9 @@ we have a dedicated glossary for Display Core
> > > at
> > > GMC
> > > Graphic Memory Controller
> > >
> > > + GPR
> > > + General Purpose Register
> > > +
> >
> > Does this refer to registers in shaders or registers in the various
> > IP
> > blocks? If this is about shaders, it would be useful to mention
> > that in
> > the context of shaders, a GPR is either SGPR or VGPR. (Those two
> > are
> > already in the glossary.)
> >
> > > GPUVM
> > > GPU Virtual Memory. This is the GPU's MMU. The GPU
> > > supports
> > > multiple
> > > virtual address spaces that can be in flight at any given
> > > time. These
> > > @@ -92,6 +104,9 @@ we have a dedicated glossary for Display Core
> > > at
> > > table for use by the kernel driver or into per process
> > > GPUVM
> > > page tables
> > > for application usage.
> > >
> > > + GWS
> > > + Global Wave Syncs
> > > +
> > > IH
> > > Interrupt Handler
> > >
> > > @@ -206,12 +221,18 @@ we have a dedicated glossary for Display
> > > Core
> > > at
> > > TC
> > > Texture Cache
> > >
> > > + TCP (AMDGPU)
> > > + Texture Cache Processing
> > > +
> > > TOC
> > > Table of Contents
> > >
> > > UMSCH
> > > User Mode Scheduler
> > >
> > > + UTCL
> > > + Universal Texture Cache Line
> > > +
> > > UVD
> > > Unified Video Decoder
> > >
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 2/5] Documentation/gpu: Add new glossary entries from UMR
2025-08-20 14:59 ` Timur Kristóf
@ 2025-08-20 22:25 ` Rodrigo Siqueira
0 siblings, 0 replies; 12+ messages in thread
From: Rodrigo Siqueira @ 2025-08-20 22:25 UTC (permalink / raw)
To: Timur Kristóf
Cc: Alex Deucher, Alex Deucher, Christian König, amd-gfx,
kernel-dev
On 08/20, Timur Kristóf wrote:
> On Tue, 2025-08-19 at 16:14 -0400, Alex Deucher wrote:
> > On Tue, Aug 19, 2025 at 3:28 PM Timur Kristóf
> > <timur.kristof@gmail.com> wrote:
> > >
> > > Hi,
> > >
> > > On Sat, 2025-08-16 at 09:31 -0600, Rodrigo Siqueira wrote:
> > > > When using UMR, a dashboard is available that displays the CPC,
> > > > CPF,
> > > > CPG, TCP, and UTCL utilization. This commit introduces the
> > > > meanings
> > > > of
> > > > those acronyms (and others) to the glossary to improve the
> > > > comprehension
> > > > of the UMR dashboard.
> > > >
> > > > Cc: Alex Deucher <alexander.deucher@amd.com>
> > > > Cc: Christian König <christian.koenig@amd.com>
> > > > Cc: Timur Kristóf <timur.kristof@gmail.com>
> > > > Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com>
> > > > ---
> > > > Documentation/gpu/amdgpu/amdgpu-glossary.rst | 21
> > > > ++++++++++++++++++++
> > > > 1 file changed, 21 insertions(+)
> > > >
> > > > diff --git a/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> > > > b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> > > > index 30812d9d53c6..eb72e6f6d4f1 100644
> > > > --- a/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> > > > +++ b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> > > > @@ -30,6 +30,15 @@ we have a dedicated glossary for Display Core
> > > > at
> > > > CP
> > > > Command Processor
> > > >
> > > > + CPC
> > > > + Command Processor Compute
> > > > +
> > > > + CPF
> > > > + Command Processor Fetch
> > > > +
> > > > + CPG
> > > > + Command Processor Graphics
> > > > +
> > >
> > > I would apprectiate a few more details here to connect these to
> > > other
> > > glossary items. Here are a few questions:
> > >
> > > - Is CPC the same as MEC?
> > > - Is CPF the same as PFP?
> > > - Is CPG the same as ME?
> >
> > CPC, CPF, and CPG are hardware blocks, MEC/PFP/ME are
> > microcontrollers. CPG contains the PFP and ME (and CE on chips which
> > support it). CPC contains MEC. CPF is another hardware block which
> > provides services to CPG and CPC.
>
> Thanks for the clarification.
>
> Siquiera - could we add that also to the glossary?
Hi Timur,
All of the acronyms mentioned are already part of the glossary, and this
commit introduces the missing ones. For more details about the
relationship between the different hardware blocks, patch number 4
provides additional information. I can add Alex's comments to patch 4 in
V2. I'll wait a little bit to see if anyone else has any comments on
patches 3, 4 and 5, before I send a V2.
Thanks
>
> Thanks,
> Timur
>
> >
> >
> > >
> > > > CPLIB
> > > > Content Protection Library
> > > >
> > > > @@ -78,6 +87,9 @@ we have a dedicated glossary for Display Core
> > > > at
> > > > GMC
> > > > Graphic Memory Controller
> > > >
> > > > + GPR
> > > > + General Purpose Register
> > > > +
> > >
> > > Does this refer to registers in shaders or registers in the various
> > > IP
> > > blocks? If this is about shaders, it would be useful to mention
> > > that in
> > > the context of shaders, a GPR is either SGPR or VGPR. (Those two
> > > are
> > > already in the glossary.)
> > >
> > > > GPUVM
> > > > GPU Virtual Memory. This is the GPU's MMU. The GPU
> > > > supports
> > > > multiple
> > > > virtual address spaces that can be in flight at any given
> > > > time. These
> > > > @@ -92,6 +104,9 @@ we have a dedicated glossary for Display Core
> > > > at
> > > > table for use by the kernel driver or into per process
> > > > GPUVM
> > > > page tables
> > > > for application usage.
> > > >
> > > > + GWS
> > > > + Global Wave Syncs
> > > > +
> > > > IH
> > > > Interrupt Handler
> > > >
> > > > @@ -206,12 +221,18 @@ we have a dedicated glossary for Display
> > > > Core
> > > > at
> > > > TC
> > > > Texture Cache
> > > >
> > > > + TCP (AMDGPU)
> > > > + Texture Cache Processing
> > > > +
> > > > TOC
> > > > Table of Contents
> > > >
> > > > UMSCH
> > > > User Mode Scheduler
> > > >
> > > > + UTCL
> > > > + Universal Texture Cache Line
> > > > +
> > > > UVD
> > > > Unified Video Decoder
> > > >
--
Rodrigo Siqueira
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/5] drm/amdgpu: Expand kernel-doc in amdgpu_ring
2025-08-18 12:30 ` Christian König
@ 2025-08-20 22:43 ` Rodrigo Siqueira
0 siblings, 0 replies; 12+ messages in thread
From: Rodrigo Siqueira @ 2025-08-20 22:43 UTC (permalink / raw)
To: Christian König
Cc: Alex Deucher, Timur Kristóf, amd-gfx, kernel-dev
On 08/18, Christian König wrote:
> On 16.08.25 17:31, Rodrigo Siqueira wrote:
> > Expand the kernel-doc about amdgpu_ring and add some tiny improvements.
> >
> > Cc: Alex Deucher <alexander.deucher@amd.com>
> > Cc: Christian König <christian.koenig@amd.com>
> > Cc: Timur Kristóf <timur.kristof@gmail.com>
> > Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com>
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 15 ++++++++++++---
> > drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 2 ++
> > 2 files changed, 14 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
> > index 6379bb25bf5c..78fd324c84e9 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
> > @@ -75,8 +75,16 @@ unsigned int amdgpu_ring_max_ibs(enum amdgpu_ring_type type)
> > * @ring: amdgpu_ring structure holding ring information
> > * @ndw: number of dwords to allocate in the ring buffer
> > *
> > - * Allocate @ndw dwords in the ring buffer (all asics).
> > - * Returns 0 on success, error on failure.
> > + * Allocate @ndw dwords in the ring buffer (it works in all ASICs). When
> > + * inspecting the code, you may encounter places where this function is called
> > + * amdgpu_ring_alloc(ring, X + Y + Z) where X, Y, and Z are integer numbers.
> > + * This is a way to show how many dwords operations will be inserted in the
> > + * ring. For example, if gfx_v9_0_wait_reg_mem(), amdgpu_ring_emit_reg_wait(),
> > + * amdgpu_ring_emit_wreg(), and amdgpu_ring_emit_fence() will be called, before
> > + * that you will see amdgpu_ring_alloc(ring, 7 + 7 + 5 + 8).
>
> Well the rest of the patch is certainly useful, but that here made me chuckle. Isn't that obvious?
Hi,
Interesting point. Tbh, it wasn't obvious to me the first time I saw it,
and I had to ask about it in one of the patch reviews. Perhaps this was
not evident to me because I'm new to this part of the code. I think a
kernel-doc in this function with this explanation can be helpful to some
other people looking into the code base for the first time, and might
also reduce one extra question to the maintainers. However, if you think
this is not necessary, I can drop it in the V2.
>
> > + *
> > + * Returns:
> > + * 0 on success, error on failure.
>
> We should probably adjust the return value of the function from -ENOMEM to -EINVAL when the number of the requested DW exceeds the maximum and document that here.
Since this will change the function return, I'll address it in another
patch.
Thanks
>
> Apart from that looks good to me.
>
> Christian.
>
> > */
> > int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned int ndw)
> > {
> > @@ -122,7 +130,8 @@ static void amdgpu_ring_alloc_reemit(struct amdgpu_ring *ring, unsigned int ndw)
> > ring->funcs->begin_use(ring);
> > }
> >
> > -/** amdgpu_ring_insert_nop - insert NOP packets
> > +/**
> > + * amdgpu_ring_insert_nop - insert NOP packets
> > *
> > * @ring: amdgpu_ring structure holding ring information
> > * @count: the number of NOP packets to insert
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> > index 7670f5d82b9e..d27dbb3c109f 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> > @@ -62,6 +62,8 @@ enum amdgpu_ring_priority_level {
> > #define AMDGPU_FENCE_FLAG_64BIT (1 << 0)
> > #define AMDGPU_FENCE_FLAG_INT (1 << 1)
> > #define AMDGPU_FENCE_FLAG_TC_WB_ONLY (1 << 2)
> > +
> > +/* Ensure the execution in case of preemption or reset */
> > #define AMDGPU_FENCE_FLAG_EXEC (1 << 3)
> >
> > #define to_amdgpu_ring(s) container_of((s), struct amdgpu_ring, sched)
>
--
Rodrigo Siqueira
^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2025-08-20 22:43 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-08-16 15:31 [PATCH 0/5] Expand kernel-doc with more generic details and info about ring buffers Rodrigo Siqueira
2025-08-16 15:31 ` [PATCH 1/5] drm/amdgpu: Expand kernel-doc in amdgpu_ring Rodrigo Siqueira
2025-08-18 12:30 ` Christian König
2025-08-20 22:43 ` Rodrigo Siqueira
2025-08-16 15:31 ` [PATCH 2/5] Documentation/gpu: Add new glossary entries from UMR Rodrigo Siqueira
2025-08-19 18:50 ` Timur Kristóf
2025-08-19 20:14 ` Alex Deucher
2025-08-20 14:59 ` Timur Kristóf
2025-08-20 22:25 ` Rodrigo Siqueira
2025-08-16 15:31 ` [PATCH 3/5] Documentation/gpu: Expand generic block information Rodrigo Siqueira
2025-08-16 15:31 ` [PATCH 4/5] Documentation/gpu: Add more information about GC Rodrigo Siqueira
2025-08-16 15:31 ` [PATCH 5/5] Documentation/gpu: Add documentation about ring buffer Rodrigo Siqueira
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