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[2001:4c4e:24d0:6700:5d2c:718b:790:18c4]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b57c53bb255sm5352131a12.5.2025.09.26.11.26.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Sep 2025 11:26:25 -0700 (PDT) From: =?UTF-8?q?Timur=20Krist=C3=B3f?= To: amd-gfx@lists.freedesktop.org Cc: alexander.deucher@amd.com, alex.hung@amd.com, harry.wentland@amd.com, siqueira@igalia.com, christian.koenig@amd.com, =?UTF-8?q?Timur=20Krist=C3=B3f?= Subject: [PATCH 0/3] More SI power management and PLL fixes Date: Fri, 26 Sep 2025 20:26:11 +0200 Message-ID: <20250926182614.26629-1-timur.kristof@gmail.com> X-Mailer: git-send-email 2.51.0 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" This series has a few minor patches to address some SI issues. When a 4K 60Hz display is connected to Tahiti or Pitcairn there is a slight flickering near the bottom of the display. Disabling MCLK switching fixes that. (Other SI parts are likely affected too, but I didn't test them thoroughly enough to say.) When enabling ASPM on Zen 4 with Tahiti and Oland, there are random hangs when the GPU usage is low. Disabling ASPM fixes that. At the moment I don't know if this is a platform-specific or GPU-specific issue and I don't think we can reasonably determine that without spending more time than we have. (Other SI parts may be affected, but I didn't test them for a long enough time to judge that.) Finally, there is a DC patch to change the minimum PLL dividers to the same value as the legacy non-DC display code. This doesn't fix any visible issue but I think it's still good to have just in case. Timur Kristóf (3): drm/amd/pm: Disable MCLK switching on SI at high pixel clocks drm/amd: Disable ASPM on SI drm/amd/display: Set stricter clock dividers on DCE 6-10 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 7 +++++++ drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c | 7 +++++++ drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c | 5 +++++ 3 files changed, 19 insertions(+) -- 2.51.0