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[2001:4c4e:24d0:6700:5d2c:718b:790:18c4]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b57c53bb255sm5352131a12.5.2025.09.26.11.26.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Sep 2025 11:26:41 -0700 (PDT) From: =?UTF-8?q?Timur=20Krist=C3=B3f?= To: amd-gfx@lists.freedesktop.org Cc: alexander.deucher@amd.com, alex.hung@amd.com, harry.wentland@amd.com, siqueira@igalia.com, christian.koenig@amd.com, =?UTF-8?q?Timur=20Krist=C3=B3f?= Subject: [PATCH 3/3] drm/amd/display: Set stricter clock dividers on DCE 6-10 Date: Fri, 26 Sep 2025 20:26:14 +0200 Message-ID: <20250926182614.26629-4-timur.kristof@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250926182614.26629-1-timur.kristof@gmail.com> References: <20250926182614.26629-1-timur.kristof@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" Set stricter dividers to stabilize the PLL's feedback loop. In practice, the actual output isn't exactly the target clock, but slowly oscillates around it. This makes it more stable. The values here are taken from the non-DC code. Signed-off-by: Timur Kristóf --- drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c index b4f5b4a6331a..00f25e2ee081 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c @@ -1700,6 +1700,13 @@ bool dce110_clk_src_construct( clk_src->cs_mask->PLL_POST_DIV_PIXCLK; calc_pll_cs_init_data.min_pll_ref_divider = 1; calc_pll_cs_init_data.max_pll_ref_divider = clk_src->cs_mask->PLL_REF_DIV; + + if (ctx->dce_version <= DCE_VERSION_10_0) { + /* Set stricter dividers to stabilize the PLL's feedback loop on old HW. */ + calc_pll_cs_init_data.min_pix_clk_pll_post_divider = 2; + calc_pll_cs_init_data.min_pll_ref_divider = 2; + } + /* when 0 use minInputPxlClkPLLFrequencyInKHz from firmwareInfo*/ calc_pll_cs_init_data.min_override_input_pxl_clk_pll_freq_khz = 0; /* when 0 use maxInputPxlClkPLLFrequencyInKHz from firmwareInfo*/ -- 2.51.0