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[2001:4c4e:24d8:e600:5908:b7d2:79c7:b6b2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-42cb7f2e454sm40537696f8f.2.2025.11.26.05.30.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Nov 2025 05:30:02 -0800 (PST) From: =?UTF-8?q?Timur=20Krist=C3=B3f?= To: =?UTF-8?q?Christian=20K=C3=B6nig?= , Alex Deucher , amd-gfx@lists.freedesktop.org Cc: =?UTF-8?q?Timur=20Krist=C3=B3f?= Subject: [PATCH 08/10] drm/amdgpu/gmc6: Delegate VM faults to soft IRQ handler ring Date: Wed, 26 Nov 2025 14:29:50 +0100 Message-ID: <20251126132952.150452-9-timur.kristof@gmail.com> X-Mailer: git-send-email 2.51.1 In-Reply-To: <20251126132952.150452-1-timur.kristof@gmail.com> References: <20251126132952.150452-1-timur.kristof@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" On old GPUs, it may be an issue that handling the interrupts from VM faults is too slow and the interrupt handler (IH) ring may overflow, which can cause an eventual hang. Delegate the processing of all VM faults to the soft IRQ handler ring. As a result, we spend much less time in the IRQ handler that interacts with the HW IH ring, which significantly reduces the chance of hangs/reboots. Signed-off-by: Timur Kristóf --- drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c index bc6a74903f4e..a8ec95f42926 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c @@ -1070,6 +1070,12 @@ static int gmc_v6_0_process_interrupt(struct amdgpu_device *adev, { u32 addr, status; + /* Delegate to the soft IRQ handler ring */ + if (adev->irq.ih_soft.enabled && entry->ih != &adev->irq.ih_soft) { + amdgpu_irq_delegate(adev, entry, 4); + return 1; + } + addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR); status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS); WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1); -- 2.51.1