From: Arun R Murthy <arun.r.murthy@intel.com>
To: "Maarten Lankhorst" <maarten.lankhorst@linux.intel.com>,
"Maxime Ripard" <mripard@kernel.org>,
"Thomas Zimmermann" <tzimmermann@suse.de>,
"David Airlie" <airlied@gmail.com>,
"Simona Vetter" <simona@ffwll.ch>,
"Harry Wentland" <harry.wentland@amd.com>,
"Leo Li" <sunpeng.li@amd.com>,
"Rodrigo Siqueira" <siqueira@igalia.com>,
"Alex Deucher" <alexander.deucher@amd.com>,
"Christian König" <christian.koenig@amd.com>,
"Jani Nikula" <jani.nikula@linux.intel.com>,
"Rodrigo Vivi" <rodrigo.vivi@intel.com>,
"Joonas Lahtinen" <joonas.lahtinen@linux.intel.com>,
"Tvrtko Ursulin" <tursulin@ursulin.net>,
"Lucas De Marchi" <lucas.demarchi@intel.com>,
"Thomas Hellström" <thomas.hellstrom@linux.intel.com>,
uma.shankar@intel.com, chaitanya.kumar.borah@intel.com,
suraj.kandpal@intel.com
Cc: dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org,
intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org,
Arun R Murthy <arun.r.murthy@intel.com>
Subject: [PATCH [RESEND] v9 15/20] drm/i915/iet: Add support to writing the IET LUT data
Date: Tue, 02 Dec 2025 11:57:09 +0530 [thread overview]
Message-ID: <20251202-dpst-v9-15-f2abb2ca2465@intel.com> (raw)
In-Reply-To: <20251202-dpst-v9-0-f2abb2ca2465@intel.com>
User created LUT can be fed back to the hardware so that the hardware
can apply this LUT data to see the enhancement in the image.
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
---
drivers/gpu/drm/i915/display/intel_histogram.c | 67 ++++++++++++++++++++++++++
drivers/gpu/drm/i915/display/intel_histogram.h | 4 ++
2 files changed, 71 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_histogram.c b/drivers/gpu/drm/i915/display/intel_histogram.c
index b42edf7dae7c0b8d083dff81c41a7ed4f7938e84..cf8aa7b04c4461629b071e49601a0e60d7609a08 100644
--- a/drivers/gpu/drm/i915/display/intel_histogram.c
+++ b/drivers/gpu/drm/i915/display/intel_histogram.c
@@ -22,6 +22,7 @@
/* Precision factor for threshold guardband */
#define HISTOGRAM_GUARDBAND_PRECISION_FACTOR 10000
#define HISTOGRAM_BIN_READ_RETRY_COUNT 5
+#define IET_SAMPLE_FORMAT_1_INT_9_FRACT 0x1000009
static bool intel_histogram_get_data(struct intel_crtc *intel_crtc)
{
@@ -227,6 +228,57 @@ int intel_histogram_update(struct intel_crtc *intel_crtc,
return 0;
}
+int intel_histogram_set_iet_lut(struct intel_crtc *intel_crtc,
+ struct drm_property_blob *blob)
+{
+ struct intel_histogram *histogram = intel_crtc->histogram;
+ struct intel_display *display = to_intel_display(intel_crtc);
+ int pipe = intel_crtc->pipe;
+ int i = 0;
+ struct drm_iet_1dlut_sample *iet;
+ struct drm_colorop *colorop = intel_crtc->base.state->color_pipeline;
+ u32 *data;
+ int ret;
+
+ if (!histogram)
+ return -EINVAL;
+
+ if (!histogram->enable) {
+ drm_err(display->drm, "histogram not enabled");
+ return -EINVAL;
+ }
+
+ data = kcalloc(iet->nr_elements, sizeof(data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ /* Set DPST_CTL Bin Reg function select to IE & wait for a vblabk */
+ intel_de_rmw(display, DPST_CTL(pipe),
+ DPST_CTL_BIN_REG_FUNC_SEL, DPST_CTL_BIN_REG_FUNC_IE);
+
+ drm_crtc_wait_one_vblank(&intel_crtc->base);
+
+ /* Set DPST_CTL Bin Register Index to 0 */
+ intel_de_rmw(display, DPST_CTL(pipe),
+ DPST_CTL_BIN_REG_MASK, DPST_CTL_BIN_REG_CLEAR);
+
+ iet = (struct drm_iet_1dlut_sample *)blob->data;
+ ret = copy_from_user(data, (uint32_t __user *)(unsigned long)iet->iet_lut,
+ sizeof(uint32_t) * iet->nr_elements);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < HISTOGRAM_IET_LENGTH; i++) {
+ intel_de_rmw(display, DPST_BIN(pipe),
+ DPST_BIN_DATA_MASK, data[i]);
+ drm_dbg_atomic(display->drm, "iet_lut[%d]=%x\n", i, data[i]);
+ }
+ drm_property_blob_put(colorop->state->data);
+ kfree(data);
+
+ return 0;
+}
+
void intel_histogram_finish(struct intel_crtc *intel_crtc)
{
struct intel_histogram *histogram = intel_crtc->histogram;
@@ -239,6 +291,8 @@ int intel_histogram_init(struct intel_crtc *crtc)
{
struct intel_histogram *histogram;
struct drm_histogram_caps *histogram_caps;
+ struct drm_iet_caps *iet_caps;
+ u32 *iet_format;
/* Allocate histogram internal struct */
histogram = kzalloc(sizeof(*histogram), GFP_KERNEL);
@@ -251,10 +305,23 @@ int intel_histogram_init(struct intel_crtc *crtc)
histogram_caps->histogram_mode = DRM_MODE_HISTOGRAM_HSV_MAX_RGB;
histogram_caps->bins_count = HISTOGRAM_BIN_COUNT;
+ iet_caps = kzalloc(sizeof(*iet_caps), GFP_KERNEL);
+ if (!iet_caps)
+ return -ENOMEM;
+
+ iet_caps->iet_mode = DRM_MODE_IET_MULTIPLICATIVE;
+ iet_caps->nr_iet_sample_formats = 1;
+ iet_caps->nr_iet_lut_entries = HISTOGRAM_IET_LENGTH;
+ iet_format = kcalloc(iet_caps->nr_iet_sample_formats, sizeof(u32),
+ GFP_KERNEL);
+ *iet_format = IET_SAMPLE_FORMAT_1_INT_9_FRACT;
+ iet_caps->iet_sample_format = *iet_format;
+
crtc->histogram = histogram;
histogram->crtc = crtc;
histogram->can_enable = false;
histogram->caps = histogram_caps;
+ histogram->iet_caps = iet_caps;
INIT_DEFERRABLE_WORK(&histogram->work,
intel_histogram_handle_int_work);
diff --git a/drivers/gpu/drm/i915/display/intel_histogram.h b/drivers/gpu/drm/i915/display/intel_histogram.h
index bd559d90e9b9fc8f5afdbc31c47702a99569b712..d4ddd99bf8c0347cdad23e3d34c14abe0c8ec7ca 100644
--- a/drivers/gpu/drm/i915/display/intel_histogram.h
+++ b/drivers/gpu/drm/i915/display/intel_histogram.h
@@ -16,9 +16,11 @@ struct intel_display;
enum pipe;
#define HISTOGRAM_BIN_COUNT 32
+#define HISTOGRAM_IET_LENGTH 33
struct intel_histogram {
struct drm_histogram_caps *caps;
+ struct drm_iet_caps *iet_caps;
struct intel_crtc *crtc;
struct delayed_work work;
bool enable;
@@ -43,6 +45,8 @@ void intel_histogram_irq_handler(struct intel_display *display, enum pipe pipe);
int intel_histogram_atomic_check(struct intel_crtc *intel_crtc);
int intel_histogram_update(struct intel_crtc *intel_crtc,
struct drm_histogram_config *config);
+int intel_histogram_set_iet_lut(struct intel_crtc *intel_crtc,
+ struct drm_property_blob *blob);
int intel_histogram_init(struct intel_crtc *intel_crtc);
void intel_histogram_finish(struct intel_crtc *intel_crtc);
--
2.25.1
next prev parent reply other threads:[~2025-12-02 6:28 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-02 6:26 [PATCH RESEND v9 00/20] Display Global Histogram Arun R Murthy
2025-12-02 6:26 ` [PATCH [RESEND] v9 01/20] DO_NOT_REVIEW: plane/crtc color pipeline Arun R Murthy
2025-12-02 6:26 ` [PATCH [RESEND] v9 02/20] drm: Define histogram structures exposed to user Arun R Murthy
2025-12-10 9:35 ` Jani Nikula
2025-12-02 6:26 ` [PATCH [RESEND] v9 03/20] drm: Add new element histogram for colorop Arun R Murthy
2025-12-02 6:26 ` [PATCH [RESEND] v9 04/20] drm/colorop: Export function to create pipeline element histogram Arun R Murthy
2025-12-02 6:26 ` [PATCH [RESEND] v9 05/20] drm: Define ImageEnhancemenT LUT structures exposed to user Arun R Murthy
2025-12-02 6:27 ` [PATCH [RESEND] v9 06/20] drm: Add new element Image EnhancemenT for colorop Arun R Murthy
2025-12-02 6:27 ` [PATCH [RESEND] v9 07/20] drm/colorop: Export function to create pipeline element iet lut Arun R Murthy
2025-12-02 6:27 ` [PATCH [RESEND] v9 08/20] drm/i915/histogram: Define registers for histogram Arun R Murthy
2025-12-02 6:27 ` [PATCH [RESEND] v9 09/20] drm/i915/histogram: Add support " Arun R Murthy
2025-12-02 6:27 ` [PATCH [RESEND] v9 10/20] drm/xe: Add histogram support to Xe builds Arun R Murthy
2025-12-02 6:27 ` [PATCH [RESEND] v9 11/20] drm/i915/histogram: histogram interrupt handling Arun R Murthy
2025-12-02 6:27 ` [PATCH DO_NOT_RTEVIEW [RESEND] v9 12/20] Plane Color Pipeline support for Intel platforms Arun R Murthy
2025-12-02 6:27 ` [PATCH [RESEND] v9 13/20] drm/i915/colorop: Add crtc color pipeline for i915 Arun R Murthy
2025-12-02 6:27 ` [PATCH [RESEND] v9 14/20] drm/i915/histogram: Hook i915 histogram with drm histogram Arun R Murthy
2025-12-02 6:27 ` Arun R Murthy [this message]
2025-12-02 6:27 ` [PATCH [RESEND] v9 16/20] drm/i915/colorop: create IET LUT properties Arun R Murthy
2025-12-02 6:27 ` [PATCH [RESEND] v9 17/20] drm/i915/crtc: Hook i915 IET LUT with the drm IET properties Arun R Murthy
2025-12-02 6:27 ` [PATCH [RESEND] v9 18/20] drm/i915/histogram: histogram delay counter doesn't reset Arun R Murthy
2025-12-02 6:27 ` [PATCH [RESEND] v9 19/20] drm/i915/histogram: Histogram changes for Display 20+ Arun R Murthy
2025-12-02 6:27 ` [PATCH [RESEND] v9 20/20] drm/i915/histogram: Enable pipe dithering Arun R Murthy
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