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Wed, 10 Dec 2025 07:14:34 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by SN1PEPF0002529E.mail.protection.outlook.com (10.167.242.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9412.4 via Frontend Transport; Wed, 10 Dec 2025 07:14:34 +0000 Received: from tr4.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Wed, 10 Dec 2025 01:14:32 -0600 From: Alex Deucher To: CC: Michael Chen , Harish Kasiviswanathan , Shaoyun.liu , "Alex Deucher" Subject: [PATCH] drm/amdgpu: Fix CP_MEC_MDBASE in multi-xcc for gfx v12_1 Date: Wed, 10 Dec 2025 02:14:04 -0500 Message-ID: <20251210071415.19983-10-alexander.deucher@amd.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251210071415.19983-1-alexander.deucher@amd.com> References: <20251210071415.19983-1-alexander.deucher@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: satlexmb08.amd.com (10.181.42.217) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002529E:EE_|DS0PR12MB8044:EE_ X-MS-Office365-Filtering-Correlation-Id: 2b19a9b4-7e9d-474e-ad41-08de37bbc591 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:satlexmb07.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(36860700013)(1800799024)(82310400026)(376014); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Dec 2025 07:14:34.5616 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2b19a9b4-7e9d-474e-ad41-08de37bbc591 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002529E.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8044 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" From: Michael Chen Need to allocate memory for MEC FW data and program registers CP_MEC_MDBASE for each XCC respectively. Signed-off-by: Michael Chen Acked-by: Harish Kasiviswanathan Reviewed-by: Shaoyun.liu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c | 192 +++++++++++++------------ 1 file changed, 98 insertions(+), 94 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c index 61ffba9a252bd..347912596a1b0 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c @@ -1887,20 +1887,18 @@ static void gfx_v12_1_xcc_cp_compute_enable(struct amdgpu_device *adev, } static int gfx_v12_1_xcc_cp_compute_load_microcode_rs64(struct amdgpu_device *adev, - int xcc_id) + uint16_t xcc_mask) { const struct gfx_firmware_header_v2_0 *mec_hdr; const __le32 *fw_ucode, *fw_data; u32 tmp, fw_ucode_size, fw_data_size; u32 i, usec_timeout = 50000; /* Wait for 50 ms */ u32 *fw_ucode_ptr, *fw_data_ptr; - int r; + int r, xcc_id; if (!adev->gfx.mec_fw) return -EINVAL; - gfx_v12_1_xcc_cp_compute_enable(adev, false, xcc_id); - mec_hdr = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data; amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); @@ -1925,7 +1923,7 @@ static int gfx_v12_1_xcc_cp_compute_load_microcode_rs64(struct amdgpu_device *ad r = amdgpu_bo_create_reserved(adev, ALIGN(fw_data_size, 64 * 1024) * - adev->gfx.mec.num_pipe_per_mec, + adev->gfx.mec.num_pipe_per_mec * NUM_XCC(xcc_mask), 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, &adev->gfx.mec.mec_fw_data_obj, &adev->gfx.mec.mec_fw_data_gpu_addr, @@ -1937,8 +1935,12 @@ static int gfx_v12_1_xcc_cp_compute_load_microcode_rs64(struct amdgpu_device *ad } memcpy(fw_ucode_ptr, fw_ucode, fw_ucode_size); - for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { - memcpy(fw_data_ptr + i * ALIGN(fw_data_size, 64 * 1024) / 4, fw_data, fw_data_size); + for_each_inst(xcc_id, xcc_mask) { + for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { + u32 offset = (xcc_id * adev->gfx.mec.num_pipe_per_mec + i) * + ALIGN(fw_data_size, 64 * 1024) / 4; + memcpy(fw_data_ptr + offset, fw_data, fw_data_size); + } } amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); @@ -1946,75 +1948,81 @@ static int gfx_v12_1_xcc_cp_compute_load_microcode_rs64(struct amdgpu_device *ad amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_data_obj); - tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_CNTL); - tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); - tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); - tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); - WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_CNTL, tmp); - - tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_DC_BASE_CNTL); - tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); - tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0); - WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_DC_BASE_CNTL, tmp); - - mutex_lock(&adev->srbm_mutex); - for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { - soc_v1_0_grbm_select(adev, 1, i, 0, 0, GET_INST(GC, xcc_id)); + for_each_inst(xcc_id, xcc_mask) { + gfx_v12_1_xcc_cp_compute_enable(adev, false, xcc_id); - WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_MDBASE_LO, - lower_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr + - i * ALIGN(fw_data_size, 64 * 1024))); - WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_MDBASE_HI, - upper_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr + - i * ALIGN(fw_data_size, 64 * 1024))); + tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_CNTL); + tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); + tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); + tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_CNTL, tmp); - WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_LO, - lower_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); - WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_HI, - upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); - } - mutex_unlock(&adev->srbm_mutex); - soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, 0)); + tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_DC_BASE_CNTL); + tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); + tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0); + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_DC_BASE_CNTL, tmp); - /* Trigger an invalidation of the L1 instruction caches */ - tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_DC_OP_CNTL); - tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1); - WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_DC_OP_CNTL, tmp); + mutex_lock(&adev->srbm_mutex); + for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { + soc_v1_0_grbm_select(adev, 1, i, 0, 0, GET_INST(GC, xcc_id)); + + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_MDBASE_LO, + lower_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr + + (xcc_id * adev->gfx.mec.num_pipe_per_mec + i) * + ALIGN(fw_data_size, 64 * 1024))); + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_MDBASE_HI, + upper_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr + + (xcc_id * adev->gfx.mec.num_pipe_per_mec + i) * + ALIGN(fw_data_size, 64 * 1024))); + + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_LO, + lower_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_HI, + upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); + } + mutex_unlock(&adev->srbm_mutex); + soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, 0)); - /* Wait for invalidation complete */ - for (i = 0; i < usec_timeout; i++) { + /* Trigger an invalidation of the L1 instruction caches */ tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_DC_OP_CNTL); - if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL, - INVALIDATE_DCACHE_COMPLETE)) - break; - udelay(1); - } - - if (i >= usec_timeout) { - dev_err(adev->dev, "failed to invalidate instruction cache\n"); - return -EINVAL; - } + tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1); + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_DC_OP_CNTL, tmp); + + /* Wait for invalidation complete */ + for (i = 0; i < usec_timeout; i++) { + tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_DC_OP_CNTL); + if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL, + INVALIDATE_DCACHE_COMPLETE)) + break; + udelay(1); + } - /* Trigger an invalidation of the L1 instruction caches */ - tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_OP_CNTL); - tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); - WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_OP_CNTL, tmp); + if (i >= usec_timeout) { + dev_err(adev->dev, "failed to invalidate instruction cache\n"); + return -EINVAL; + } - /* Wait for invalidation complete */ - for (i = 0; i < usec_timeout; i++) { + /* Trigger an invalidation of the L1 instruction caches */ tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_OP_CNTL); - if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, - INVALIDATE_CACHE_COMPLETE)) - break; - udelay(1); - } + tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_OP_CNTL, tmp); + + /* Wait for invalidation complete */ + for (i = 0; i < usec_timeout; i++) { + tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_OP_CNTL); + if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, + INVALIDATE_CACHE_COMPLETE)) + break; + udelay(1); + } - if (i >= usec_timeout) { - dev_err(adev->dev, "failed to invalidate instruction cache\n"); - return -EINVAL; - } + if (i >= usec_timeout) { + dev_err(adev->dev, "failed to invalidate instruction cache\n"); + return -EINVAL; + } - gfx_v12_1_xcc_set_mec_ucode_start_addr(adev, xcc_id); + gfx_v12_1_xcc_set_mec_ucode_start_addr(adev, xcc_id); + } return 0; } @@ -2411,42 +2419,43 @@ static int gfx_v12_1_xcc_kcq_resume(struct amdgpu_device *adev, return r; } -static int gfx_v12_1_xcc_cp_resume(struct amdgpu_device *adev, - int xcc_id) +static int gfx_v12_1_xcc_cp_resume(struct amdgpu_device *adev, uint16_t xcc_mask) { - int r, i; + int r, i, xcc_id; struct amdgpu_ring *ring; - if (!(adev->flags & AMD_IS_APU)) - gfx_v12_1_xcc_enable_gui_idle_interrupt(adev, false, xcc_id); - if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { /* legacy firmware loading */ - r = gfx_v12_1_xcc_cp_compute_load_microcode_rs64(adev, xcc_id); + r = gfx_v12_1_xcc_cp_compute_load_microcode_rs64(adev, xcc_mask); if (r) return r; } - gfx_v12_1_xcc_cp_set_doorbell_range(adev, xcc_id); + for_each_inst(xcc_id, xcc_mask) { + if (!(adev->flags & AMD_IS_APU)) + gfx_v12_1_xcc_enable_gui_idle_interrupt(adev, false, xcc_id); - gfx_v12_1_xcc_cp_compute_enable(adev, true, xcc_id); + gfx_v12_1_xcc_cp_set_doorbell_range(adev, xcc_id); - if (adev->enable_mes_kiq && adev->mes.kiq_hw_init) - r = amdgpu_mes_kiq_hw_init(adev, xcc_id); - else - r = gfx_v12_1_xcc_kiq_resume(adev, xcc_id); - if (r) - return r; + gfx_v12_1_xcc_cp_compute_enable(adev, true, xcc_id); - r = gfx_v12_1_xcc_kcq_resume(adev, xcc_id); - if (r) - return r; + if (adev->enable_mes_kiq && adev->mes.kiq_hw_init) + r = amdgpu_mes_kiq_hw_init(adev, xcc_id); + else + r = gfx_v12_1_xcc_kiq_resume(adev, xcc_id); + if (r) + return r; - for (i = 0; i < adev->gfx.num_compute_rings; i++) { - ring = &adev->gfx.compute_ring[i + xcc_id * adev->gfx.num_compute_rings]; - r = amdgpu_ring_test_helper(ring); + r = gfx_v12_1_xcc_kcq_resume(adev, xcc_id); if (r) return r; + + for (i = 0; i < adev->gfx.num_compute_rings; i++) { + ring = &adev->gfx.compute_ring[i + xcc_id * adev->gfx.num_compute_rings]; + r = amdgpu_ring_test_helper(ring); + if (r) + return r; + } } return 0; @@ -3923,14 +3932,9 @@ static int gfx_v12_1_xcp_resume(void *handle, uint32_t inst_mask) } } - tmp_mask = inst_mask; - for_each_inst(i, tmp_mask) { - r = gfx_v12_1_xcc_cp_resume(adev, i); - if (r) - return r; - } + r = gfx_v12_1_xcc_cp_resume(adev, inst_mask); - return 0; + return r; } static int gfx_v12_1_xcp_suspend(void *handle, uint32_t inst_mask) -- 2.52.0