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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:satlexmb07.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(1800799024)(376014)(36860700013)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Dec 2025 07:14:43.6742 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 81fa37be-614e-49ab-d1d6-08de37bbcaff X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000252A2.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6739 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" From: Hawking Zhang To acommandate specific interrupt source for gfx v12_1 Signed-off-by: Hawking Zhang Reviewed-by: Likun Gao Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c | 8 +- drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c | 4 +- .../include/ivsrcid/gfx/irqsrcs_gfx_12_1_0.h | 136 ++++++++++++++++++ 3 files changed, 142 insertions(+), 6 deletions(-) create mode 100644 drivers/gpu/drm/amd/include/ivsrcid/gfx/irqsrcs_gfx_12_1_0.h diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c index 96ca3648205d6..6a4ecded103aa 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c @@ -37,7 +37,7 @@ #include "gc/gc_12_1_0_offset.h" #include "gc/gc_12_1_0_sh_mask.h" #include "soc24_enum.h" -#include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h" +#include "ivsrcid/gfx/irqsrcs_gfx_12_1_0.h" #include "soc15.h" #include "clearstate_gfx12.h" @@ -1170,21 +1170,21 @@ static int gfx_v12_1_sw_init(struct amdgpu_ip_block *ip_block) /* EOP Event */ r = amdgpu_irq_add_id(adev, SOC_V1_0_IH_CLIENTID_GRBM_CP, - GFX_11_0_0__SRCID__CP_EOP_INTERRUPT, + GFX_12_1_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq); if (r) return r; /* Privileged reg */ r = amdgpu_irq_add_id(adev, SOC_V1_0_IH_CLIENTID_GRBM_CP, - GFX_11_0_0__SRCID__CP_PRIV_REG_FAULT, + GFX_12_1_0__SRCID__CP_PRIV_REG_FAULT, &adev->gfx.priv_reg_irq); if (r) return r; /* Privileged inst */ r = amdgpu_irq_add_id(adev, SOC_V1_0_IH_CLIENTID_GRBM_CP, - GFX_11_0_0__SRCID__CP_PRIV_INSTR_FAULT, + GFX_12_1_0__SRCID__CP_PRIV_INSTR_FAULT, &adev->gfx.priv_inst_irq); if (r) return r; diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c b/drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c index e3963675bfac0..fe0e84b45cf4b 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c @@ -32,7 +32,7 @@ #include "gc/gc_12_1_0_offset.h" #include "gc/gc_12_1_0_sh_mask.h" -#include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h" +#include "ivsrcid/gfx/irqsrcs_gfx_12_1_0.h" #include "soc15_common.h" #include "soc15.h" @@ -1278,7 +1278,7 @@ static int sdma_v7_1_sw_init(struct amdgpu_ip_block *ip_block) /* SDMA trap event */ r = amdgpu_irq_add_id(adev, SOC_V1_0_IH_CLIENTID_GFX, - GFX_11_0_0__SRCID__SDMA_TRAP, + GFX_12_1_0__SRCID__SDMA_TRAP, &adev->sdma.trap_irq); if (r) return r; diff --git a/drivers/gpu/drm/amd/include/ivsrcid/gfx/irqsrcs_gfx_12_1_0.h b/drivers/gpu/drm/amd/include/ivsrcid/gfx/irqsrcs_gfx_12_1_0.h new file mode 100644 index 0000000000000..9fe5466e94183 --- /dev/null +++ b/drivers/gpu/drm/amd/include/ivsrcid/gfx/irqsrcs_gfx_12_1_0.h @@ -0,0 +1,136 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef __IRQSRCS_GFX_12_1_0_H__ +#define __IRQSRCS_GFX_12_1_0_H__ + +/* 0x0 UTCL2 has encountered a fault scenario */ +#define GFX_12_1_0__SRCID__UTCL2_FAULT 0 +/* 0x1 UTCL2 has encountered a retry scenario */ +#define GFX_12_1_0__SRCID__UTCL2_RETRY 1 +/* 0x2 UTCL2 for data poisoning */ +#define GFX_12_1_0__SRCID__UTCL2_DATA_POISONING 2 +/* 0x30 SDMA atomic*_rtn ops complete */ +#define GFX_12_1_0__SRCID__SDMA_ATOMIC_RTN_DONE 48 +/* 0x31 Trap */ +#define GFX_12_1_0__SRCID__SDMA_TRAP 49 +/* 0x32 SRBM write Protection */ +#define GFX_12_1_0__SRCID__SDMA_SRBMWRITE 50 +/* 0x33 Context Empty */ +#define GFX_12_1_0__SRCID__SDMA_CTXEMPTY 51 +/* 0x34 SDMA New Run List */ +#define GFX_12_1_0__SRCID__SDMA_PREEMPT 52 +/* 0x35 sdma mid - command buffer preempt interrupt */ +#define GFX_12_1_0__SRCID__SDMA_IB_PREEMPT 53 +/* 0x36 Doorbell BE invalid */ +#define GFX_12_1_0__SRCID__SDMA_DOORBELL_INVALID 54 +/* 0x37 Queue hang or Command timeout */ +#define GFX_12_1_0__SRCID__SDMA_QUEUE_HANG 55 +/* 0x38 SDMA atomic CMPSWAP loop timeout */ +#define GFX_12_1_0__SRCID__SDMA_ATOMIC_TIMEOUT 56 +/* 0x39 SRBM read poll timeout */ +#define GFX_12_1_0__SRCID__SDMA_POLL_TIMEOUT 57 +/* 0x3A Page retry timeout after UTCL2 return nack = 1 */ +#define GFX_12_1_0__SRCID__SDMA_PAGE_TIMEOUT 58 +/* 0x3B Page Null from UTCL2 when nack = 2 */ +#define GFX_12_1_0__SRCID__SDMA_PAGE_NULL 59 +/* 0x3C Page Fault Error from UTCL2 when nack = 3 */ +#define GFX_12_1_0__SRCID__SDMA_PAGE_FAULT 60 +/* 0x3D MC or SEM address in VM hole */ +#define GFX_12_1_0__SRCID__SDMA_INVALID_ADDR 61 +/* 0x3E ECC Error */ +#define GFX_12_1_0__SRCID__SDMA_ECC 62 +/* 0x3F SDMA Frozen */ +#define GFX_12_1_0__SRCID__SDMA_FROZEN 63 +/* 0x40 SRAM ECC Error */ +#define GFX_12_1_0__SRCID__SDMA_SRAM_ECC 64 +/* 0x41 GPF(Sem incomplete timeout) */ +#define GFX_12_1_0__SRCID__SDMA_SEM_INCOMPLETE_TIMEOUT 65 +/* 0x42 Semaphore wait fail timeout */ +#define GFX_12_1_0__SRCID__SDMA_SEM_WAIT_FAIL_TIMEOUT 66 +/* 0x43 Wptr less than Rptr in active queue */ +#define GFX_12_1_0__SRCID__SDMA_INVALID_RB_PTR 67 +/* 0x44 BE command exception */ +#define GFX_12_1_0__SRCID__SDMA_BE_EXCEPTION 68 +/* 0x46 User fence. inherit from gfx v12_0 for gfx user queue */ +#define GFX_12_1_0__SRCID__SDMA_FENCE 70 +/* 0xB0 CP_INTERRUPT pkt in RB */ +#define GFX_12_1_0__SRCID__CP_RB_INT_PKT 176 +/* 0xB1 CP_INTERRUPT pkt in IB1 */ +#define GFX_12_1_0__SRCID__CP_IB1_INT_PKT 177 +/* 0xB2 CP_INTERRUPT pkt in IB2 */ +#define GFX_12_1_0__SRCID__CP_IB2_INT_PKT 178 +/* 0xB3 DMA Watch Interrupt */ +#define GFX_12_1_0__SRCID__CP_DMA_WATCH_INTERRUPT 179 +/* 0xB4 PM4 Pkt Rsvd Bits Error */ +#define GFX_12_1_0__SRCID__CP_PM4_PKT_RSVD_BIT_ERROR 180 +/* 0xB5 End-of-Pipe Interrupt */ +#define GFX_12_1_0__SRCID__CP_EOP_INTERRUPT 181 +/* 0xB7 Bad Opcode Error */ +#define GFX_12_1_0__SRCID__CP_BAD_OPCODE_ERROR 183 +/* 0xB8 Privileged Register Fault */ +#define GFX_12_1_0__SRCID__CP_PRIV_REG_FAULT 184 +/* 0xB9 Privileged Instr Fault */ +#define GFX_12_1_0__SRCID__CP_PRIV_INSTR_FAULT 185 +/* 0xBA Wait Memory Semaphore Fault (Sync Object Fault) */ +#define GFX_12_1_0__SRCID__CP_WAIT_MEM_SEM_FAULT 186 +/* 0xBB Context Empty Interrupt */ +#define GFX_12_1_0__SRCID__CP_CTX_EMPTY_INTERRUPT 187 +/* 0xBC Context Busy Interrupt */ +#define GFX_12_1_0__SRCID__CP_CTX_BUSY_INTERRUPT 188 +/* 0xC0 CP.ME Wait_Reg_Mem Poll Timeout */ +#define GFX_12_1_0__SRCID__CP_ME_WAIT_REG_MEM_POLL_TIMEOUT 192 +/* 0xC1 Surface Probe Fault Signal Incomplete */ +#define GFX_12_1_0__SRCID__CP_SIG_INCOMPLETE 193 +/* 0xC2 Preemption Ack-wledge */ +#define GFX_12_1_0__SRCID__CP_PREEMPT_ACK 194 +/* 0xC3 General Protection Fault (GPF) */ +#define GFX_12_1_0__SRCID__CP_GPF 195 +/* 0xC4 GDS Alloc Error */ +#define GFX_12_1_0__SRCID__CP_GDS_ALLOC_ERROR 196 +/* 0xC5 ECC Error */ +#define GFX_12_1_0__SRCID__CP_ECC_ERROR 197 +/* 0xC8 Unattached VM Doorbell Received */ +#define GFX_12_1_0__SRCID__CP_VM_DOORBELL 200 +/* 0xC9 ECC FUE Error */ +#define GFX_12_1_0__SRCID__CP_FUE_ERROR 201 +/* 0xCA Suspend Completion Interrupt */ +#define GFX_12_1_0__SRCID__CP_SUSPEAND_REQ_INTERRUPT 202 +/* 0xCB Resume Completion Interrupt */ +#define GFX_12_1_0__SRCID__CP_RESUME_REQ_INTERRUPT 203 +/* 0xCA RLC Streaming Perf Monitor Interrupt + * ContextID[15:0] each bit indicates poison is seen on respecive indexed VMID + * Ex: ContextID[3] == 1 means VMID-3 encountered poison consumption + * ContextID[16] == 1 indicates that complete VF need to reset with FLR */ +#define GFX_12_1_0__SRCID__RLC_STRM_PERF_MONITOR_INTERRUPT 202 +/* 0xCB RLC Poison Interrupt */ +#define GFX_12_1_0__SRCID__RLC_POISON_INTERRUPT 203 +/* 0xE7 High on ContextID[0] - nHT Error; ContextID[1] - illegal Opcode Error */ +#define GFX_12_1_0__SRCID__PMR_EA_ERROR_INTERRUPT 231 +/* 0xE8 CRead timeout error */ +#define GFX_12_1_0__SRCID__GRBM_RD_TIMEOUT_ERROR 232 +/* 0xE9 Register GUI Idle */ +#define GFX_12_1_0__SRCID__GRBM_REG_GUI_IDLE 233 +/* 0xEF SQ Interrupt (ttrace wrap, errors) */ +#define GFX_12_1_0__SRCID__SQ_INTERRUPT_ID 239 + +#endif -- 2.52.0