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Thu, 8 Jan 2026 08:49:02 -0600 From: Alex Deucher To: CC: Alex Deucher Subject: [PATCH 27/42] drm/amdgpu: mark fences with errors before ring reset Date: Thu, 8 Jan 2026 09:48:28 -0500 Message-ID: <20260108144843.493816-28-alexander.deucher@amd.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260108144843.493816-1-alexander.deucher@amd.com> References: <20260108144843.493816-1-alexander.deucher@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF0000ECD7:EE_|SA1PR12MB5637:EE_ X-MS-Office365-Filtering-Correlation-Id: 81b948f1-e006-4a13-3d1c-08de4ec5165b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700013|376014|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?pboqGOCy3rSOaAE08YZZucw6flCPgrgTlUNIepupN9sbca4zN+ztVuW32DqW?= =?us-ascii?Q?lXKdKENUbGnGZOeXiFMYInsjXQLcKtA6VZOZt13/XBlpC1TPiEizilT8beU0?= =?us-ascii?Q?0bibATMr5isq+nFyODn5GNKt8k2vaAxi4saC0rBWU21BhSsplASJSPrgVPBp?= =?us-ascii?Q?2Z4XkxuZ5O/E8iLQ6AvojAl2jjKc2poU5LyLL/sMIXyM6GWM3ST3jDMd0h9V?= =?us-ascii?Q?1xXhqIJELiNgK+4J7aPpJZJ1VrKywMlY44cyHTx2xn0bBesvKKwa1zFTnyHP?= =?us-ascii?Q?o0LY+wrfblQxPo8XifY8Yq37gZwsIl/KlA5mkrX5TA9OeJaxFz70pIdR8CeB?= =?us-ascii?Q?CpeOQZNPKVs0AWNJJrHprjq3pWc8XGP71D//vJoYNEtbI1kGuo2TgcvOPcu2?= =?us-ascii?Q?Gi0OYIdv743addteidOV6xcvY03IRwpFm/ejc3fy+qolVKPYIgBT6C5EXbej?= =?us-ascii?Q?V8Q4gFPtXYPXXtlN8ud5MW951SM+wrwCJF/RLBogfnEU2xYGEOEsvKNcRTUX?= =?us-ascii?Q?071CoR7Z+wJEoAa+t1CsxMxIoR9pHqYSiRzWSxRkda9AhnF8XRYwV7auyyJG?= =?us-ascii?Q?vhxto7+MFJJtUgYUFlpm2wwsoDqrTxsBRaU0nRIwJFSsZjoHHJMA+dLVHDkL?= =?us-ascii?Q?+rflqVlSwqhedVtgDJ0Ho1cfPV2jl4vo3U9Mnm7Xx8GGPgAmUS3Rm0y+9hdy?= =?us-ascii?Q?f+1zn5q7TFyz8FPKlADnHN/OvrzggYO1bU13GxTfNhCgjE3JMyZXRU0oWB3Y?= =?us-ascii?Q?c7yhlgMJVpVYRS9KUwa/+ipVgpFi/KhkqWRNEaYzT5J+xcWbxZFKJNQjHSkC?= =?us-ascii?Q?epsqFRXd65/ceg3xbTDpWOmekS9SpwditUx2zAVAyJa+Y/VjlxWDw2FoeJA/?= =?us-ascii?Q?oLBixAOj9OTX7c33CAZDxoZF6rXyA8hrsPGNJj2Li1L89hBrid8JefQTyrSs?= =?us-ascii?Q?jRAeSGqKJ+/1UgI58fW5PdHvUfOI2fv6hTe2ZM9t8Gg15h0VhrNJ0h6ajMRi?= =?us-ascii?Q?DQvjz118YgZ2mAr9LFeniUD2ASniEJWX2Qx8NCbw4fqq3zVQJpRN1RBLtFMS?= =?us-ascii?Q?9kqvxbB3KUKjRrSsVCxr7qS4ybh67K0cRx2LRPQBTkP9KgKzMb6FSYVBIb0N?= =?us-ascii?Q?iQs4KVv2X8hYoBdc2/QPn96BzNGkZEjFkCYZsSO4B68sqgrKWepJkRfO3YyW?= =?us-ascii?Q?JlkLrym7nSDPnNtSj0sMAfW43np1OLnzJJgGkcJ3gNd3IaG8ovil4O9goc4d?= =?us-ascii?Q?W2IOw3RvmeMzEZpo4mZLY8WHPT8j8SLcrEv6hxsNMTpNB32OfXI2FqPmDaHj?= =?us-ascii?Q?Fob0/SBSUXSGDYwsSr3yVDIGfDmU5vlJAzdFovMoY+yZgsrGw3IXC8wA4I6O?= =?us-ascii?Q?orVtkeb4IQjR/4ZaNyeQKodIEMM4Q/KeZ5OT15CpIF+/YCaA+XnfrzjdabGd?= =?us-ascii?Q?Rz/vPqbWfqR7ONytR3hcehanSEA0T4Ax300rVAaRJTrme8g3iOFQn/Uofzn1?= =?us-ascii?Q?xetZhw3WYW/CKuzHUVohSucq4D1HzTkvjzvb4HdCI0sErBlP1VgAweWLdPiQ?= =?us-ascii?Q?HZ6/ljjGCOaH/Wq0Hw8=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:satlexmb07.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(36860700013)(376014)(1800799024)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Jan 2026 14:49:12.3349 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 81b948f1-e006-4a13-3d1c-08de4ec5165b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000ECD7.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB5637 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" Mark fences with errors before we reset the rings as we may end up signalling fences as part of the reset sequence. The error needs to be set before the fence is signalled. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c index 600e6bb98af7a..5defdebd7091e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c @@ -872,6 +872,10 @@ void amdgpu_ring_reset_helper_begin(struct amdgpu_ring *ring, drm_sched_wqueue_stop(&ring->sched); /* back up the non-guilty commands */ amdgpu_ring_backup_unprocessed_commands(ring, guilty_fence); + /* signal the guilty fence and set an error on all fences from the context */ + if (guilty_fence) + amdgpu_fence_driver_guilty_force_completion(guilty_fence); + } int amdgpu_ring_reset_helper_end(struct amdgpu_ring *ring, @@ -885,9 +889,6 @@ int amdgpu_ring_reset_helper_end(struct amdgpu_ring *ring, if (r) return r; - /* signal the guilty fence and set an error on all fences from the context */ - if (guilty_fence) - amdgpu_fence_driver_guilty_force_completion(guilty_fence); /* Re-emit the non-guilty commands */ if (ring->ring_backup_entries_to_copy) { amdgpu_ring_alloc_reemit(ring, ring->ring_backup_entries_to_copy); -- 2.52.0