From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4AFBFD38FEC for ; Wed, 14 Jan 2026 16:47:51 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 60C9C10E639; Wed, 14 Jan 2026 16:47:50 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (1024-bit key; unprotected) header.d=amd.com header.i=@amd.com header.b="eF/rkvDo"; dkim-atps=neutral Received: from SA9PR02CU001.outbound.protection.outlook.com (mail-southcentralusazon11013027.outbound.protection.outlook.com [40.93.196.27]) by gabe.freedesktop.org (Postfix) with ESMTPS id 56DC410E62A for ; Wed, 14 Jan 2026 16:47:48 +0000 (UTC) ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=eX6VjAAKTdga4L2/W0/R1KoaNGQ7v46vVJ1G1yFk+WuPhvo3srbFxj4rBllCP+y4qrNqa8T3J7MhqzMX9jljm0BduWf3uRragXT+GA1RU3qcaSigsk5SrO6ee9qPxn0B3mUVD7hVgTfZANPhJjkpxgRYC2GsFCbfzDZzFAk3cQA6a0MUWTtvHPuwtfqED5oSyzT+elgpJtJyNgd5432Q3otl++0Ky/vaFtujc1B6YyvjSbSqeQI/+86ou/8vogS17fOwv4M+ZegWeMMeL38mX7qG7T3kt9hEd7XZolsjdeIs1GMGTeL4rJ6aeOp8ehfegiLpjDcEdjCykIv2ArnkQA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=un3yQDsKyxkwSlfbBuUhSBUZeOH5osWw25N6NAKF88E=; b=qCGwtNxW1Ibc7BVdoBxqkYFt+IGajXcoHvgr5fI2PuCNtXiEk8jsR49ulkWR+8zqHbTbhVMuQP9WEy1nDM/hKXs8XlI/l3zZqm8OuU33DWtdlImOc5V+qD1AI/Y90hsFnvbjET2aLZImuH672XNG/hy4OtSPbeVMrv6xdPUkxWxFIdvx6qhC3f+WYB6dY2xffRCOKyT2as27MNoCdw6mXhqjzE8xpNZvzzVsUCbnArwfxY2HlHZE7JPBuSMhLTnxPuSXfL7P6nm6JylYOxMj26JsUM/pYq1LlwSiMijaQlf1plJLxwosTGnIioViEJor8T+FRFvd95cYx9xHxq8/qw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.freedesktop.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=un3yQDsKyxkwSlfbBuUhSBUZeOH5osWw25N6NAKF88E=; b=eF/rkvDokWomDLtUshFC8c63KId1+w/MxLR4qfHoN3H5VUkLnPLDgvSXdByrWaaaFcNsG9n24+8R8H128HLmzyoIBMjfEYkvXU4/9lv8bv0+0LzhbvFXDLloz+q8YGZzDaRZ19mzMAS/4UceJfUJtkyZiuw+J8Gh04/SC7ZoIbc= Received: from PH8P221CA0012.NAMP221.PROD.OUTLOOK.COM (2603:10b6:510:2d8::17) by CH3PR12MB9731.namprd12.prod.outlook.com (2603:10b6:610:253::5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9499.6; Wed, 14 Jan 2026 16:47:44 +0000 Received: from CY4PEPF0000E9D6.namprd05.prod.outlook.com (2603:10b6:510:2d8:cafe::d1) by PH8P221CA0012.outlook.office365.com (2603:10b6:510:2d8::17) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9520.4 via Frontend Transport; Wed, 14 Jan 2026 16:47:43 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by CY4PEPF0000E9D6.mail.protection.outlook.com (10.167.241.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9520.1 via Frontend Transport; Wed, 14 Jan 2026 16:47:43 +0000 Received: from SATLEXMB04.amd.com (10.181.40.145) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.17; Wed, 14 Jan 2026 10:47:38 -0600 Received: from satlexmb08.amd.com (10.181.42.217) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Wed, 14 Jan 2026 10:47:38 -0600 Received: from p8.amd.com (10.180.168.240) by satlexmb08.amd.com (10.181.42.217) with Microsoft SMTP Server id 15.2.2562.17 via Frontend Transport; Wed, 14 Jan 2026 10:47:38 -0600 From: Alex Deucher To: CC: Alex Deucher Subject: [PATCH 05/42] drm/amdgpu/gfx8: switch to using job for IBs Date: Wed, 14 Jan 2026 11:46:50 -0500 Message-ID: <20260114164727.15367-6-alexander.deucher@amd.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260114164727.15367-1-alexander.deucher@amd.com> References: <20260114164727.15367-1-alexander.deucher@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain Received-SPF: None (SATLEXMB04.amd.com: alexander.deucher@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D6:EE_|CH3PR12MB9731:EE_ X-MS-Office365-Filtering-Correlation-Id: bf863915-e91d-458d-6054-08de538ca378 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700013|1800799024|376014|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?NEQbKvimDLbBmkIrUYYq2qi9jleBlkJWu+IU23UWwal1SsrK8J5Zc7oHSu+b?= =?us-ascii?Q?b4Xuy0n+naVm5+4ebtyUIZTt3m8iqYV1e7m1fC1rSOeXJLLtL0W6xlXqf1h3?= =?us-ascii?Q?uu2roHjsaA6qiFYBoCRErOKjeN/cadA5WO6iBLo6DL5Zo04bYJuBDTLAivF0?= =?us-ascii?Q?p9IW83IuOQetK8K7ROjTcopidVnAfAhFc4+T12Zp3K+cTl6fXvWBiKnCVHFN?= =?us-ascii?Q?WBn33WPhxWuieosXA6FPOE7BLdfMy9KiI2JERQxiR1MqykhI4T1lkW/rOfrV?= =?us-ascii?Q?7C3kvBICRkjkZlFJGB2pHa3WSUCv3noCGFGHZFUfb8yxNPYH68ezRHpvZkKx?= =?us-ascii?Q?1axoDHBEsYOJSS4o//o7eOYuUza2fkQWHr2Wdj5mfgGEX8uEdIXOXfGeZK1P?= =?us-ascii?Q?kF8e6Gu/df7Qzpr5m2Nmmn/lBrqnLYnjC052FSHV+FsSFllOE6lM1PkFNQxJ?= =?us-ascii?Q?WoMFjd8wbq9R49vd6I+lZeOs6rk67c56tJPPZsNSWK29HNm+h0pnUSS7k5rR?= =?us-ascii?Q?NFlqj1Yqem67ol9POz1a4Q7Qtn5pGmDGWBQX9UTN18QVxb0//+eR3kK+aRBl?= =?us-ascii?Q?/u896jm01y/ZKLAh9UrJZl8eggixhjeX38ts0l3O+Dyq74o4I2+7wD9In/b5?= =?us-ascii?Q?whQxbAP45Qsg4TZabmsNlvOtkQBoc12GwWpbEKTss1QFvBAb9Gwr/Cf+DURy?= =?us-ascii?Q?7f3rgSjjKcKHHdBAmLCzTTyMAwOA/F103WXvGU7XmWJeT5N28Jx8MIvH3vwK?= =?us-ascii?Q?aHHudQ3v2cEUuFF9DLxAfRrkHdDB/sydLb0UX5dYtErhhQAGG8+JFEMsRENk?= =?us-ascii?Q?PzGT2bXqXgeMBffLJIq4Qkwrq7fq7w4asTGNBdVW4M0JbjiQCvNfsvUGvXUh?= =?us-ascii?Q?cQi6PZqF7rxHUTD5BhTnbTGMtcNed47Awg0/EExREmuJ4b6rd1hb9YAyGY29?= =?us-ascii?Q?7Ei6U380gtE96YEnnL3MqUpIpM03+lKkOY9tNwU58Vstm54e9Ahs8wSMKFJy?= =?us-ascii?Q?K+yleY8SYVCp4/3H0ZwEZUN+BRUFjT8Zw0Tr1YkDX9hCvhuwH8FjVnaWkfZ0?= =?us-ascii?Q?yYupur0doSOwXTG+ts9BbU61Erafijp7ZJC+s6ZNF86i4DlEjQ329RDPbt6P?= =?us-ascii?Q?zFvnvoNHSaKJRCElo5+mlgfHeDxrFIaiNB7E80HZ8GBmgltFAnGO9bNwzBTV?= =?us-ascii?Q?xm80FRjGzVLImXysTW06kvfv5/F9TDi6GTGDKQkkci0fnApn11TP9v4HN4Pr?= =?us-ascii?Q?V6JX5kdtDU1xxLDuay0ORe1RHrCOjf3Zf7U8BH7VM7RzEWdEKwcC7fyQvK6c?= =?us-ascii?Q?l8D3Lz0q+CwBBGrxELI0H9d1RaxQB+e9QcsCG8IfLPPwMaoVv/ByBiGFCOQC?= =?us-ascii?Q?SBxGRVLB6SeXu4pfdt5LlnmIy10GYW/vvII/T7/GjGMmNa6wHwhl7AH6sLPz?= =?us-ascii?Q?mAEqQd1yxvNb10Wdbx/6P3GpwA2/DrIXepyjioWu2Q5hKvfN5N3EHbwvsRyW?= =?us-ascii?Q?KcxrW/3JSClRv5y5YvUFXU4dvAxbNOcr2rKJn4SwayMt7Q/AYlzl0DLcvQ/V?= =?us-ascii?Q?E08P8QWZVEWwiyT15a1Qo3z1DqTo3V4sF1LL3jDU3gzAtJVvkxJAkqarV8lg?= =?us-ascii?Q?yQFiL1ItfgykfTlbdd2KrfnHnHyjr/H4aSfIo/KBRlklKmPb468jWPYNAKr/?= =?us-ascii?Q?LuqCZQ=3D=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:satlexmb07.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(36860700013)(1800799024)(376014)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jan 2026 16:47:43.5415 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bf863915-e91d-458d-6054-08de538ca378 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D6.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9731 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" Switch to using a job structure for IBs. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 139 +++++++++++++------------- 1 file changed, 72 insertions(+), 67 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index a6b4c8f41dc11..4736216cd0211 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -868,9 +868,9 @@ static int gfx_v8_0_ring_test_ring(struct amdgpu_ring *ring) static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) { struct amdgpu_device *adev = ring->adev; - struct amdgpu_ib ib; + struct amdgpu_job *job; + struct amdgpu_ib *ib; struct dma_fence *f = NULL; - unsigned int index; uint64_t gpu_addr; uint32_t tmp; @@ -882,22 +882,26 @@ static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) gpu_addr = adev->wb.gpu_addr + (index * 4); adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); - memset(&ib, 0, sizeof(ib)); - r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib); + r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, 20, + AMDGPU_IB_POOL_DIRECT, &job, + AMDGPU_KERNEL_JOB_ID_GFX_RING_TEST); if (r) goto err1; - ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); - ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; - ib.ptr[2] = lower_32_bits(gpu_addr); - ib.ptr[3] = upper_32_bits(gpu_addr); - ib.ptr[4] = 0xDEADBEEF; - ib.length_dw = 5; + ib = &job->ibs[0]; + ib->ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); + ib->ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; + ib->ptr[2] = lower_32_bits(gpu_addr); + ib->ptr[3] = upper_32_bits(gpu_addr); + ib->ptr[4] = 0xDEADBEEF; + ib->length_dw = 5; - r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); - if (r) + r = amdgpu_job_submit_direct(job, ring, &f); + if (r) { + amdgpu_job_free(job); goto err2; + } r = dma_fence_wait_timeout(f, false, timeout); if (r == 0) { @@ -914,7 +918,6 @@ static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) r = -EINVAL; err2: - amdgpu_ib_free(&ib, NULL); dma_fence_put(f); err1: amdgpu_device_wb_free(adev, index); @@ -1474,7 +1477,8 @@ static const u32 sec_ded_counter_registers[] = static int gfx_v8_0_do_edc_gpr_workarounds(struct amdgpu_device *adev) { struct amdgpu_ring *ring = &adev->gfx.compute_ring[0]; - struct amdgpu_ib ib; + struct amdgpu_job *job; + struct amdgpu_ib *ib; struct dma_fence *f = NULL; int r, i; u32 tmp; @@ -1505,106 +1509,108 @@ static int gfx_v8_0_do_edc_gpr_workarounds(struct amdgpu_device *adev) total_size += sizeof(sgpr_init_compute_shader); /* allocate an indirect buffer to put the commands in */ - memset(&ib, 0, sizeof(ib)); - r = amdgpu_ib_get(adev, NULL, total_size, - AMDGPU_IB_POOL_DIRECT, &ib); + r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, total_size, + AMDGPU_IB_POOL_DIRECT, &job, + AMDGPU_KERNEL_JOB_ID_RUN_SHADER); if (r) { drm_err(adev_to_drm(adev), "failed to get ib (%d).\n", r); return r; } + ib = &job->ibs[0]; /* load the compute shaders */ for (i = 0; i < ARRAY_SIZE(vgpr_init_compute_shader); i++) - ib.ptr[i + (vgpr_offset / 4)] = vgpr_init_compute_shader[i]; + ib->ptr[i + (vgpr_offset / 4)] = vgpr_init_compute_shader[i]; for (i = 0; i < ARRAY_SIZE(sgpr_init_compute_shader); i++) - ib.ptr[i + (sgpr_offset / 4)] = sgpr_init_compute_shader[i]; + ib->ptr[i + (sgpr_offset / 4)] = sgpr_init_compute_shader[i]; /* init the ib length to 0 */ - ib.length_dw = 0; + ib->length_dw = 0; /* VGPR */ /* write the register state for the compute dispatch */ for (i = 0; i < ARRAY_SIZE(vgpr_init_regs); i += 2) { - ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1); - ib.ptr[ib.length_dw++] = vgpr_init_regs[i] - PACKET3_SET_SH_REG_START; - ib.ptr[ib.length_dw++] = vgpr_init_regs[i + 1]; + ib->ptr[ib->length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1); + ib->ptr[ib->length_dw++] = vgpr_init_regs[i] - PACKET3_SET_SH_REG_START; + ib->ptr[ib->length_dw++] = vgpr_init_regs[i + 1]; } /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */ - gpu_addr = (ib.gpu_addr + (u64)vgpr_offset) >> 8; - ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); - ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START; - ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr); - ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr); + gpu_addr = (ib->gpu_addr + (u64)vgpr_offset) >> 8; + ib->ptr[ib->length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); + ib->ptr[ib->length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START; + ib->ptr[ib->length_dw++] = lower_32_bits(gpu_addr); + ib->ptr[ib->length_dw++] = upper_32_bits(gpu_addr); /* write dispatch packet */ - ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3); - ib.ptr[ib.length_dw++] = 8; /* x */ - ib.ptr[ib.length_dw++] = 1; /* y */ - ib.ptr[ib.length_dw++] = 1; /* z */ - ib.ptr[ib.length_dw++] = + ib->ptr[ib->length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3); + ib->ptr[ib->length_dw++] = 8; /* x */ + ib->ptr[ib->length_dw++] = 1; /* y */ + ib->ptr[ib->length_dw++] = 1; /* z */ + ib->ptr[ib->length_dw++] = REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1); /* write CS partial flush packet */ - ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0); - ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4); + ib->ptr[ib->length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0); + ib->ptr[ib->length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4); /* SGPR1 */ /* write the register state for the compute dispatch */ for (i = 0; i < ARRAY_SIZE(sgpr1_init_regs); i += 2) { - ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1); - ib.ptr[ib.length_dw++] = sgpr1_init_regs[i] - PACKET3_SET_SH_REG_START; - ib.ptr[ib.length_dw++] = sgpr1_init_regs[i + 1]; + ib->ptr[ib->length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1); + ib->ptr[ib->length_dw++] = sgpr1_init_regs[i] - PACKET3_SET_SH_REG_START; + ib->ptr[ib->length_dw++] = sgpr1_init_regs[i + 1]; } /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */ - gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8; - ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); - ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START; - ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr); - ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr); + gpu_addr = (ib->gpu_addr + (u64)sgpr_offset) >> 8; + ib->ptr[ib->length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); + ib->ptr[ib->length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START; + ib->ptr[ib->length_dw++] = lower_32_bits(gpu_addr); + ib->ptr[ib->length_dw++] = upper_32_bits(gpu_addr); /* write dispatch packet */ - ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3); - ib.ptr[ib.length_dw++] = 8; /* x */ - ib.ptr[ib.length_dw++] = 1; /* y */ - ib.ptr[ib.length_dw++] = 1; /* z */ - ib.ptr[ib.length_dw++] = + ib->ptr[ib->length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3); + ib->ptr[ib->length_dw++] = 8; /* x */ + ib->ptr[ib->length_dw++] = 1; /* y */ + ib->ptr[ib->length_dw++] = 1; /* z */ + ib->ptr[ib->length_dw++] = REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1); /* write CS partial flush packet */ - ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0); - ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4); + ib->ptr[ib->length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0); + ib->ptr[ib->length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4); /* SGPR2 */ /* write the register state for the compute dispatch */ for (i = 0; i < ARRAY_SIZE(sgpr2_init_regs); i += 2) { - ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1); - ib.ptr[ib.length_dw++] = sgpr2_init_regs[i] - PACKET3_SET_SH_REG_START; - ib.ptr[ib.length_dw++] = sgpr2_init_regs[i + 1]; + ib->ptr[ib->length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1); + ib->ptr[ib->length_dw++] = sgpr2_init_regs[i] - PACKET3_SET_SH_REG_START; + ib->ptr[ib->length_dw++] = sgpr2_init_regs[i + 1]; } /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */ - gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8; - ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); - ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START; - ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr); - ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr); + gpu_addr = (ib->gpu_addr + (u64)sgpr_offset) >> 8; + ib->ptr[ib->length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); + ib->ptr[ib->length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START; + ib->ptr[ib->length_dw++] = lower_32_bits(gpu_addr); + ib->ptr[ib->length_dw++] = upper_32_bits(gpu_addr); /* write dispatch packet */ - ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3); - ib.ptr[ib.length_dw++] = 8; /* x */ - ib.ptr[ib.length_dw++] = 1; /* y */ - ib.ptr[ib.length_dw++] = 1; /* z */ - ib.ptr[ib.length_dw++] = + ib->ptr[ib->length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3); + ib->ptr[ib->length_dw++] = 8; /* x */ + ib->ptr[ib->length_dw++] = 1; /* y */ + ib->ptr[ib->length_dw++] = 1; /* z */ + ib->ptr[ib->length_dw++] = REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1); /* write CS partial flush packet */ - ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0); - ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4); + ib->ptr[ib->length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0); + ib->ptr[ib->length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4); /* shedule the ib on the ring */ - r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); + r = amdgpu_job_submit_direct(job, ring, &f); if (r) { drm_err(adev_to_drm(adev), "ib submit failed (%d).\n", r); + amdgpu_job_free(job); goto fail; } @@ -1629,7 +1635,6 @@ static int gfx_v8_0_do_edc_gpr_workarounds(struct amdgpu_device *adev) RREG32(sec_ded_counter_registers[i]); fail: - amdgpu_ib_free(&ib, NULL); dma_fence_put(f); return r; -- 2.52.0