From: Jay Cornwall <jay.cornwall@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: Lancelot Six <lancelot.six@amd.com>,
Alexey Kondratiev <Alexey.Kondratiev@amd.com>,
Jay Cornwall <jay.cornwall@amd.com>,
"Vladimir Indic" <vladimir.indic@amd.com>
Subject: [PATCH 5/5] drm/amdkfd: Do not include VGPR MSBs in saved PC during save
Date: Fri, 16 Jan 2026 14:39:32 -0600 [thread overview]
Message-ID: <20260116203932.988704-6-jay.cornwall@amd.com> (raw)
In-Reply-To: <20260116203932.988704-1-jay.cornwall@amd.com>
From: Lancelot Six <lancelot.six@amd.com>
The current trap handler uses the top bits of ttmp1 to store a copy of
sq_wave_mode.*vgpr_msb (except for src2_vgpr_msb). This is so the
effective values in sq_wave_mode can be cleared to ensure correct
behavior of the trap handler.
When saving sq_wave_mode, the trap handler correctly rebuilds the
expected value (with *vgpr_msb restored), so the save area is correct.
However, the PC itself is copied from ttmp[0:1], which contains the
wave's PC as well as the saved MSBs.
The debugger reads the PC from the save area and is confused when non-0
values from VGPR_MSBs are present.
This patch fixes this by saving the PC in the save area's PC slot, not
the composite of the PC and VGPR_MSBs. On restore, the VGPR_MSBs are
restored from sq_wave_mode.
Signed-off-by: Lancelot Six <lancelot.six@amd.com>
Tested-by: Alexey Kondratiev <Alexey.Kondratiev@amd.com>
Reviewed-by: Jay Cornwall <jay.cornwall@amd.com>
Cc: Vladimir Indic <vladimir.indic@amd.com>
---
drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h | 6 +++---
drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx12.asm | 2 +-
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
index 9bb7fb6a83ed..39bdc98b8b6d 100644
--- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
+++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
@@ -3760,8 +3760,8 @@ static const uint32_t cwsr_trap_gfx12_hex[] = {
0xb8faf804, 0x8b7a847a,
0x91788478, 0x8c787a78,
0xd7610002, 0x0000fa6c,
- 0x807d817d, 0x917aff6d,
- 0x80000000, 0xd7610002,
+ 0x807d817d, 0x8b7aff6d,
+ 0x0000ffff, 0xd7610002,
0x0000fa7a, 0x807d817d,
0xd7610002, 0x0000fa6e,
0x807d817d, 0xd7610002,
@@ -4848,7 +4848,7 @@ static const uint32_t cwsr_trap_gfx12_1_0_hex[] = {
0x9178ff78, 0x0001000c,
0x8c787a78, 0xd7610002,
0x0000fa6c, 0x807d817d,
- 0x917aff6d, 0x80000000,
+ 0x8b7aff6d, 0x01ffffff,
0xd7610002, 0x0000fa7a,
0x807d817d, 0xd7610002,
0x0000fa6e, 0x807d817d,
diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx12.asm b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx12.asm
index ccc61f60ceb3..c33e7660d8f4 100644
--- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx12.asm
+++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx12.asm
@@ -544,7 +544,7 @@ L_SAVE_HWREG:
s_or_b32 s_save_state_priv, s_save_state_priv, s_save_tmp
write_hwreg_to_v2(s_save_pc_lo)
- s_andn2_b32 s_save_tmp, s_save_pc_hi, S_SAVE_PC_HI_FIRST_WAVE_MASK
+ s_and_b32 s_save_tmp, s_save_pc_hi, ADDRESS_HI32_MASK
write_hwreg_to_v2(s_save_tmp)
write_hwreg_to_v2(s_save_exec_lo)
#if WAVE32_ONLY
--
2.34.1
prev parent reply other threads:[~2026-01-16 20:40 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-16 20:39 [PATCH 0/5] drm/amdkfd: Trap handler fixes and gfx12.1 support Jay Cornwall
2026-01-16 20:39 ` [PATCH 1/5] drm/amdkfd: Sync trap handler binary with source Jay Cornwall
2026-01-20 22:34 ` Lancelot SIX
2026-01-21 10:27 ` Indic, Vladimir
2026-01-16 20:39 ` [PATCH 2/5] drm/amdkfd: Fix scalar load ordering in gfx12.1 trap handler Jay Cornwall
2026-01-20 22:38 ` Lancelot SIX
2026-01-21 10:32 ` Indic, Vladimir
2026-01-16 20:39 ` [PATCH 3/5] drm/amdkfd: gfx12.1 cluster barrier context save workaround Jay Cornwall
2026-01-20 23:27 ` Lancelot SIX
2026-01-21 10:37 ` Indic, Vladimir
2026-01-16 20:39 ` [PATCH 4/5] drm/amdkfd: gfx12.1 trap handler support for expert scheduling mode Jay Cornwall
2026-01-20 23:30 ` Lancelot SIX
2026-01-21 10:46 ` Indic, Vladimir
2026-01-16 20:39 ` Jay Cornwall [this message]
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