From: "Timur Kristóf" <timur.kristof@gmail.com>
To: amd-gfx@lists.freedesktop.org, Alexander.Deucher@amd.com,
Christian.Koenig@amd.com,
Mario Limonciello <mario.limonciello@amd.com>,
Ivan Lipski <ivan.lipski@amd.com>, Alex Hung <alex.hung@amd.com>,
Prike Liang <Prike.Liang@amd.com>
Cc: "Timur Kristóf" <timur.kristof@gmail.com>
Subject: [PATCH 1/5] drm/amd/pm: Fix si_dpm mmCG_THERMAL_INT setting
Date: Mon, 19 Jan 2026 21:36:22 +0100 [thread overview]
Message-ID: <20260119203626.16070-2-timur.kristof@gmail.com> (raw)
In-Reply-To: <20260119203626.16070-1-timur.kristof@gmail.com>
Use WREG32 to write mmCG_THERMAL_INT.
This is a direct access register.
Fixes: 841686df9f7d ("drm/amdgpu: add SI DPM support (v4)")
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
---
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
index 9bdcd4e2aeb2..f7c2b1d206b6 100644
--- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
+++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
@@ -7600,12 +7600,12 @@ static int si_dpm_set_interrupt_state(struct amdgpu_device *adev,
case AMDGPU_IRQ_STATE_DISABLE:
cg_thermal_int = RREG32_SMC(mmCG_THERMAL_INT);
cg_thermal_int |= CG_THERMAL_INT__THERM_INT_MASK_HIGH_MASK;
- WREG32_SMC(mmCG_THERMAL_INT, cg_thermal_int);
+ WREG32(mmCG_THERMAL_INT, cg_thermal_int);
break;
case AMDGPU_IRQ_STATE_ENABLE:
cg_thermal_int = RREG32_SMC(mmCG_THERMAL_INT);
cg_thermal_int &= ~CG_THERMAL_INT__THERM_INT_MASK_HIGH_MASK;
- WREG32_SMC(mmCG_THERMAL_INT, cg_thermal_int);
+ WREG32(mmCG_THERMAL_INT, cg_thermal_int);
break;
default:
break;
@@ -7617,12 +7617,12 @@ static int si_dpm_set_interrupt_state(struct amdgpu_device *adev,
case AMDGPU_IRQ_STATE_DISABLE:
cg_thermal_int = RREG32_SMC(mmCG_THERMAL_INT);
cg_thermal_int |= CG_THERMAL_INT__THERM_INT_MASK_LOW_MASK;
- WREG32_SMC(mmCG_THERMAL_INT, cg_thermal_int);
+ WREG32(mmCG_THERMAL_INT, cg_thermal_int);
break;
case AMDGPU_IRQ_STATE_ENABLE:
cg_thermal_int = RREG32_SMC(mmCG_THERMAL_INT);
cg_thermal_int &= ~CG_THERMAL_INT__THERM_INT_MASK_LOW_MASK;
- WREG32_SMC(mmCG_THERMAL_INT, cg_thermal_int);
+ WREG32(mmCG_THERMAL_INT, cg_thermal_int);
break;
default:
break;
--
2.52.0
next prev parent reply other threads:[~2026-01-19 20:36 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-19 20:36 [PATCH 0/5] Various SI power management fixes Timur Kristóf
2026-01-19 20:36 ` Timur Kristóf [this message]
2026-01-19 20:36 ` [PATCH 2/5] drm/amd/pm: Don't clear SI SMC table when setting power limit Timur Kristóf
2026-01-19 20:36 ` [PATCH 3/5] drm/amd/pm: Workaround SI powertune issue on Radeon 430 (v2) Timur Kristóf
2026-01-19 20:36 ` [PATCH 4/5] drm/amd/pm: Return -EOPNOTSUPP when can't read power limit Timur Kristóf
2026-01-19 20:36 ` [PATCH 5/5] drm/amd/pm: Correct comment above power2_cap attributes Timur Kristóf
2026-01-20 20:32 ` Alex Deucher
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