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Mon, 26 Jan 2026 14:07:57 -0600 From: Alex Deucher To: CC: Alex Deucher , Yifan Zhang Subject: [PATCH 03/12] drm/amdgpu/gfx10: handle gfxoff in interrupt set functions Date: Mon, 26 Jan 2026 15:07:38 -0500 Message-ID: <20260126200747.13527-3-alexander.deucher@amd.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260126200747.13527-1-alexander.deucher@amd.com> References: <20260126200747.13527-1-alexander.deucher@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001EF:EE_|DS0PR12MB8344:EE_ X-MS-Office365-Filtering-Correlation-Id: 496190f9-a342-4738-5914-08de5d1699b5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|36860700013|376014|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?wFGlL4lUqAvYZepTiD6pHk3DMwqVKpTakkLBTe29EGTBADeNPq8hkon+y06T?= =?us-ascii?Q?m29jiofDCtvdprbmfK9WZhB/E4r/jikSWObcfqeImPlc2ifnAQ9iWkW5tqhy?= =?us-ascii?Q?zaaWWY/dgOFUWufjhH59+U68eE8G95aGUUph95HUTHl+4eNvgFepAsm7J+T+?= =?us-ascii?Q?oDBfnNpHJd2dtVQeykj1O4yYvrfxHztGXC+u/l5XKgHrBN4Kn0sZXigTxPqH?= =?us-ascii?Q?hLzKPA+g+cwfGwPpdYC1feYlG7TW4l/+T4seQMqJ/KZQ3msjIunIfs49K4Kc?= =?us-ascii?Q?GCRLrkH0hLAcjYEKGGoiLbbQJ6Xxo7U/OCv12auv4t/rkom6v9EOSnsRMfHa?= =?us-ascii?Q?jvCnbbhQf3hzEKCagYXllMyGA0bcmz7lFEvZGX/uPIoKI64/4KAwTzr8Q+vX?= =?us-ascii?Q?7xwWs4Oqa17fAXNFh/TmMC5XZ63PICjmj8goyWB+MpMRtVTjzWKAzqW9I0+s?= =?us-ascii?Q?U8lVysaBKTj8hiJyoesc636Y2R5q5IzfvNRWwOQ55L7YH43Gl9ep9mT0P81A?= =?us-ascii?Q?1Uwq3zB7YSiFDEeIBFgJQ8Z2O9BuGG4Ag9Ug3znzUL1+wUShuSOIa8Y1UXur?= =?us-ascii?Q?3XqRLKiLYpFedYZ3dzuznwpAEtJui15lwOzXgGfja2MA+tDOWvwb8leRcm+N?= =?us-ascii?Q?FBzkR1AYpoEX+4yN7eGaMAB7Fddzkdh3fKTfCFV1ZXN7F9dcuQe/cAMbbu0I?= =?us-ascii?Q?bHiojFENPa6QfUfV6E6BHe5mLoV1CpwfHNqqJ0Ez8GGsTLDT0k6Vsaa0iGYd?= =?us-ascii?Q?+j9Xo3WGHZtjCc9+/h29gzWEOVGAUE+czjAdhlMQv0b5qnXDEq7+Q+E+j/sk?= =?us-ascii?Q?+Ah+cyzlgMKSJgcbRAEv70+llV0+0Hri7cTRX8yLwoJpPx/BOuQoVgFAu8Ca?= =?us-ascii?Q?FNGvSLGELH+RwnVnHDuDIVEnqpK07V0139jqL1yIJesNgLH7qU1yJ2TkLcl/?= =?us-ascii?Q?NFsBaWWAaXD3ffehoZoDzB1V36zO/H10j6Cvytudu0V23tfK8R1VRmQiU0B2?= =?us-ascii?Q?d7BQTNkjsx9lbpUGeYxg3WvDt0jgoDR6EEDy5l5WWw5kNy8kWstEAVHe3PIq?= =?us-ascii?Q?LrBuxxHy/0EgvRxevhlA5o3sJTTAYXrxvt6qAPU0gLc3eik6kW1UHHVzXFDE?= =?us-ascii?Q?DYXhEMxrlLWWlFDrIjkLlilviY8apBBO3uW0gCHb6Z3yoTUEKD3wqammQU92?= =?us-ascii?Q?aImsibtCN17fIdCIvUoANR4K6aARLYF3fkyc0jMtkafVxGoPxwrPaM3YsKYT?= =?us-ascii?Q?NrIxiX418zOAsreuYlrsTSeOyyN8nF9XSMvD7UTo0KgWxsLLflPH1nu1w3UZ?= =?us-ascii?Q?jX5WWuDOOPtCyD3/xUn7mKCOGZ3nwnYXAwCcDuCS1C+d1yTdA2ALrbu/hb3s?= =?us-ascii?Q?7zOSKvL5HPPy/wIusq90Z0bbUft/TCEmdX/tMPxuXyU9mJzH3/veR8V9ItGX?= =?us-ascii?Q?eKf1ZODm6ABduaWj4GSaySPz5eTDW/pY6d4v7SPOosq9T3chaBIfDMisSdZn?= =?us-ascii?Q?rBJvqa2F+wHAnjhX888fQJYJfyuWcXK5Df0gBSc3SGImmucS8lvqrvZqZfRl?= =?us-ascii?Q?QF7ibmjEw9GDiENj/Q4pwJdH0chlXSICKngMoUNqgNJdLS3u2c8qbTQUY69L?= =?us-ascii?Q?NdD6hssx0Nmfla71+fb+3Il6VJYFDI8q5POQChAFP18VrZByISHmttbtrDq8?= =?us-ascii?Q?v3Eekw=3D=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:satlexmb07.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(1800799024)(36860700013)(376014)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jan 2026 20:07:58.1553 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 496190f9-a342-4738-5914-08de5d1699b5 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001EF.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8344 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" Need to make sure gfxoff is disallowed when we touch GC registers over MMIO. Cc: Yifan Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 496121bdc1de1..31dd0aeef509d 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -9141,6 +9141,7 @@ static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev, unsigned int type, enum amdgpu_interrupt_state state) { + amdgpu_gfx_off_ctrl(adev, false); switch (type) { case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); @@ -9175,6 +9176,8 @@ static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev, default: break; } + amdgpu_gfx_off_ctrl(adev, true); + return 0; } @@ -9226,6 +9229,7 @@ static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev, u32 cp_int_cntl_reg, cp_int_cntl; int i, j; + amdgpu_gfx_off_ctrl(adev, false); switch (state) { case AMDGPU_IRQ_STATE_DISABLE: case AMDGPU_IRQ_STATE_ENABLE: @@ -9260,6 +9264,7 @@ static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev, default: break; } + amdgpu_gfx_off_ctrl(adev, true); return 0; } @@ -9272,6 +9277,7 @@ static int gfx_v10_0_set_bad_op_fault_state(struct amdgpu_device *adev, u32 cp_int_cntl_reg, cp_int_cntl; int i, j; + amdgpu_gfx_off_ctrl(adev, false); switch (state) { case AMDGPU_IRQ_STATE_DISABLE: case AMDGPU_IRQ_STATE_ENABLE: @@ -9306,6 +9312,8 @@ static int gfx_v10_0_set_bad_op_fault_state(struct amdgpu_device *adev, default: break; } + amdgpu_gfx_off_ctrl(adev, true); + return 0; } @@ -9317,6 +9325,7 @@ static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev, u32 cp_int_cntl_reg, cp_int_cntl; int i, j; + amdgpu_gfx_off_ctrl(adev, false); switch (state) { case AMDGPU_IRQ_STATE_DISABLE: case AMDGPU_IRQ_STATE_ENABLE: @@ -9337,6 +9346,7 @@ static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev, default: break; } + amdgpu_gfx_off_ctrl(adev, true); return 0; } @@ -9410,6 +9420,7 @@ static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev, uint32_t tmp, target; struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring); + amdgpu_gfx_off_ctrl(adev, false); if (ring->me == 1) target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); else @@ -9444,6 +9455,8 @@ static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev, BUG(); /* kiq only support GENERIC2_INT now */ break; } + amdgpu_gfx_off_ctrl(adev, true); + return 0; } -- 2.52.0