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Mon, 26 Jan 2026 14:07:59 -0600 From: Alex Deucher To: CC: Alex Deucher , Yifan Zhang Subject: [PATCH 07/12] drm/amdgpu/gfx11: handle gfxoff in interrupt set functions Date: Mon, 26 Jan 2026 15:07:42 -0500 Message-ID: <20260126200747.13527-7-alexander.deucher@amd.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260126200747.13527-1-alexander.deucher@amd.com> References: <20260126200747.13527-1-alexander.deucher@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001EA:EE_|LV8PR12MB9406:EE_ X-MS-Office365-Filtering-Correlation-Id: b5930959-eb7f-4570-e085-08de5d169af9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700013|376014|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?QcN2QihWgMowoRVwotsF3/mL16NnlEbppV88lQagtjHUz+/0/5RBCRhzsQTm?= =?us-ascii?Q?Rq3ZU3IHjQ07N+j+hHkFDoHJHHOpkZGSjSnLSNQcqqYL+7esao3TCVRAPLVN?= =?us-ascii?Q?+3FrwQ5LbjR/XUpHH13+n8uUlPbNcwZdw6Usf954H7HM84mew2v3geLJSTWY?= =?us-ascii?Q?GqazuErk7AFhi38hCLVIXSk529Liymo7kYTjvspul+tMr7+h7tJZ4vBBS93N?= =?us-ascii?Q?ZFeRPOqDw5nA9+UYrGhPmTF1py43f4UhMN7tk6efooLzo7ZjQeQAfaQVEWUS?= =?us-ascii?Q?+IBYyu6Mq/Sh84pO+k2TijhBff61EHMuvDtyEtiNemH3/GQO86W1NyH9XaJD?= =?us-ascii?Q?/uHC6ply1LjnLeqDrflL0eU+H5zSJsmybk58YQpxMtzIUp0O0R5cszr2xG7N?= =?us-ascii?Q?cA5hXTYapt9VRRlXy88H1tt9nkjAc13kfBK23BjwUyaP5IWiR6VWvobFYnME?= =?us-ascii?Q?Lp/XTu3bwhttZQIEAsTIrW3jcZ6QrxvrWaYfK/O6XmF04LqFsSrOn9fpzojq?= =?us-ascii?Q?qUs7U98fz2K4IUiIKiIe4ZEV+Gh+3eDQNzMfN52owrG/xt1OAlbNkolCA+/p?= =?us-ascii?Q?51IFd4HlswHNO5iHUyih+Cl9nl8OCAD6sLWgLaQ/iJjfLCQP//RTJFoSwahY?= =?us-ascii?Q?mXkVNvnIaR++qbL0HLwNXOMvtrSzNVorrQXn3QUtwJ2Fhf4iYpanRabFUJVE?= =?us-ascii?Q?7y99n+gYvfp3Kgdh6VvQa4u4ZD8/voAdBa43IuXvlfCU5kbPUcxfKoxONaFq?= =?us-ascii?Q?Chmt6Q5D7ocOk9iklUtD1R/fp4G/QA772Ax4YnWSzH9I9nghCpNyYjskKnhP?= =?us-ascii?Q?5p4DRTvG9LI3cByjCJeh75hwxjkDhG7hmELKgj2MZorJZmM0QsztJk0LAb3a?= =?us-ascii?Q?S6ABWIACW48GC38REiQHW2xYbkPlXFRnUrnTINZx6Lz2YMtPeu4xKcBMlYL3?= =?us-ascii?Q?wpAYbOkJPJAB6+RwyiVwWMFph1D3yHgzWb+Lu/nwpQ6pY05Sus5tObOxg8w2?= =?us-ascii?Q?4yRFXmqbcmvVbE2gUMC/Z8kgHmdwTL+MeGF9K1b6mMP5UXxGJ+YbhALdC5Td?= =?us-ascii?Q?0+IZ/3cYR0x8ym5857j01rSteKsc+B0UNZ9QxkyBTC1p0Vg1c0xEE4RVCQ/T?= =?us-ascii?Q?57wyHbiq0jm6N9von4OprKbL2ftvKz0B+dZS4cfXlPe/fQGElVYzAjl4lhTv?= =?us-ascii?Q?YOO1CqSFropZ5sUeqWEEpo9k+g4jCCj3UVf1AxRQUlWV2fZFUBg5IhPgut7f?= =?us-ascii?Q?itdgor9az7eBm6yyEkU5pwjCkWGoS5ZlOidkPt8qRg2gAsqEV11W2ToZQJIt?= =?us-ascii?Q?AWVpyhW6DfldIUs/pUg79d1pm1/VKgMBs4szA6XSowql40NDLq6QwfFjAr4m?= =?us-ascii?Q?Qdc2MFsP6mgZFkuUvf+tlL3Ae21yPB4HTiClF+jTkE/ktocb7YxtNi5bwdb6?= =?us-ascii?Q?FyfYl4BPJl67OzMQZdctHr5mAtWYa8rHyYbwlH6AR2qGkV1FJtio21zL/j6q?= =?us-ascii?Q?4OmOGxI7Sxf9SRCoP+d/Gp0czyCS17jIqQRTKElebkoNNKlSF5IODZN8zHb/?= =?us-ascii?Q?WUo8vMChXq+bICtYCUTezgY9H59QJModE5Jc8Zd9R/spwezQcodBpSVYlB17?= =?us-ascii?Q?e2ZFsoNL8B+wGcQopDtnTrC5trZO6VijTy5m82ui06QbEwmSBNkfy79EqMTc?= =?us-ascii?Q?2o7KaA=3D=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:satlexmb07.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(36860700013)(376014)(1800799024)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jan 2026 20:08:00.3196 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b5930959-eb7f-4570-e085-08de5d169af9 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001EA.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9406 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" Need to make sure gfxoff is disallowed when we touch GC registers over MMIO. Cc: Yifan Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index 5ad2516a60240..ddbb92825fac3 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -6421,6 +6421,7 @@ static int gfx_v11_0_set_eop_interrupt_state(struct amdgpu_device *adev, unsigned type, enum amdgpu_interrupt_state state) { + amdgpu_gfx_off_ctrl(adev, false); switch (type) { case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: gfx_v11_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); @@ -6443,6 +6444,8 @@ static int gfx_v11_0_set_eop_interrupt_state(struct amdgpu_device *adev, default: break; } + amdgpu_gfx_off_ctrl(adev, true); + return 0; } @@ -6507,6 +6510,7 @@ static int gfx_v11_0_set_priv_reg_fault_state(struct amdgpu_device *adev, u32 cp_int_cntl_reg, cp_int_cntl; int i, j; + amdgpu_gfx_off_ctrl(adev, false); switch (state) { case AMDGPU_IRQ_STATE_DISABLE: case AMDGPU_IRQ_STATE_ENABLE: @@ -6541,6 +6545,7 @@ static int gfx_v11_0_set_priv_reg_fault_state(struct amdgpu_device *adev, default: break; } + amdgpu_gfx_off_ctrl(adev, true); return 0; } @@ -6553,6 +6558,7 @@ static int gfx_v11_0_set_bad_op_fault_state(struct amdgpu_device *adev, u32 cp_int_cntl_reg, cp_int_cntl; int i, j; + amdgpu_gfx_off_ctrl(adev, false); switch (state) { case AMDGPU_IRQ_STATE_DISABLE: case AMDGPU_IRQ_STATE_ENABLE: @@ -6587,6 +6593,8 @@ static int gfx_v11_0_set_bad_op_fault_state(struct amdgpu_device *adev, default: break; } + amdgpu_gfx_off_ctrl(adev, true); + return 0; } @@ -6598,6 +6606,7 @@ static int gfx_v11_0_set_priv_inst_fault_state(struct amdgpu_device *adev, u32 cp_int_cntl_reg, cp_int_cntl; int i, j; + amdgpu_gfx_off_ctrl(adev, false); switch (state) { case AMDGPU_IRQ_STATE_DISABLE: case AMDGPU_IRQ_STATE_ENABLE: @@ -6618,6 +6627,7 @@ static int gfx_v11_0_set_priv_inst_fault_state(struct amdgpu_device *adev, default: break; } + amdgpu_gfx_off_ctrl(adev, true); return 0; } -- 2.52.0