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Mon, 26 Jan 2026 14:08:00 -0600 From: Alex Deucher To: CC: Alex Deucher , Yifan Zhang Subject: [PATCH 09/12] drm/amdgpu/gfx12: handle gfxoff in interrupt set functions Date: Mon, 26 Jan 2026 15:07:44 -0500 Message-ID: <20260126200747.13527-9-alexander.deucher@amd.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260126200747.13527-1-alexander.deucher@amd.com> References: <20260126200747.13527-1-alexander.deucher@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001E9:EE_|CH2PR12MB4136:EE_ X-MS-Office365-Filtering-Correlation-Id: 228608a4-dcc7-4d60-563f-08de5d169fcc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|82310400026|376014|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?NWBhxc8VgOxjnxPQXukOSFoAqVsfAmM1i7nrJoSjLrDw9DjDT+DanSHEnPFb?= =?us-ascii?Q?zg9H8rn+oOX4JHpMQxVkrW+yCakczUjKWwB9yj3eaK1kC0Mv6YanWvUL1l4s?= =?us-ascii?Q?MsrJTM63aVKC+leU5kvK/b5w5YIoBcrtUnKZQ0Oqk3RmGEiS4aDEVNr+YF/N?= =?us-ascii?Q?m8xSXxZycVnWf1EVCYPuA3Zccm9Vh1tQ926nL1gNpzsK2SVkbt1V8gPKJZja?= =?us-ascii?Q?CAstI4IpC4Riu/q+LQ5+SIsiSZwfpPci5G8WO7eWJG5Ml44o9D111g/YDyWj?= =?us-ascii?Q?pN7brxkZmPqPuykuGJkeu4/Vn7DJz6aK7NgF71q3jnFr7yrq+f0E2PNv2p60?= =?us-ascii?Q?hrGItMriHMWKyneSwTO+lw+iaC/wCxcIkXY0Mdzy3TfoC3P4+YAtq5i3xsu/?= =?us-ascii?Q?wOO/WaO5I0ZZOqgSIPH1n2TC2O+YzuRJfKkTBA/PkQmreHy9YxCecJqCtT4e?= =?us-ascii?Q?QqwywTRNY9K4+eRIu2VWydVDs3ORVYesf6LQWpvYC2a+ThTFCa43kGgYCtzV?= =?us-ascii?Q?1cgD4zyzJFge/bDls0tRbenxIX0QM/oBk/1EiHTQtlqZsfFolD+5GJ8xO8XH?= =?us-ascii?Q?eH+aFHkZ6jlKxLk0E6oDSpHGtgV36jUThSxjM2OQtTVatFd8eOgPAs6taelx?= =?us-ascii?Q?IkWOYl3D9kChNXkf9oGGZEoHZweb28/7GengLUtXtu8DTNj5XU7kGkeCCfel?= =?us-ascii?Q?od1+hF0cjVtPv2EsZPwiix1yW8C5VeP05wBY0E4vT2XEcRxvzZnT2zs4ivro?= =?us-ascii?Q?8cWpJcL9QRuhzSL8uDacjYROqcLzEs4LH0KjVlRaKn7UTbX0Cq7C+RhKai6I?= =?us-ascii?Q?17kD5haK5LsK1v6EZbgFJk6PZPRjWK2yRBkeA7GaIpCTWtj3r1H4+6kYvFGC?= =?us-ascii?Q?I1hbgbgbtLjNM+cHJtjyhCJVyzHvedPxBR+saUsUME4gxnWvDF65rB1Nxirj?= =?us-ascii?Q?cQpH+uSbL1gUnJOO2SGS/cRDFSCHbn4o9wZRCaWw1H1IFf47fAJq8E1luO8E?= =?us-ascii?Q?KNhtr0q9epRjYw3b+s/ftX8U7cBvrpxLN3cjW8suD5mDdEhwMf6vQ4jdZKWs?= =?us-ascii?Q?UI48hpdZ+11MgrOA6UATy8+oWE9heoj01uJUnbH5AhzbjB8ukCdEkCECslOh?= =?us-ascii?Q?qTzFGYldrpC7fNzbQ+NRQvPah8/AYmoxOgYh5feQKeH8vmhL1Mub0SyKJRUG?= =?us-ascii?Q?23Rj7GYfd4LzBTBnYgfo5DmE8qGOjcUzK7tD939QLP6qxeFBTViQCbVoUhmt?= =?us-ascii?Q?wKilGgfBaC5LTvFxWqiGn/1f9yCtgiwKgU004ASqNM9V5o24Bb4vo+DhL+bE?= =?us-ascii?Q?feDz2l8WBHBSd16TiZxMZdwptzlAVZTV0+e7XpJY5x63sqnzJIK0OWdkv81S?= =?us-ascii?Q?w1NzovK1lcrHbUPlCtoCklR7lkXp1bZm/Wa1tOXUaQz8GgB1bL77VJLPOb+R?= =?us-ascii?Q?Wss8h+1JAMUWZzJ4hynMXtd8i9wOSXUBwxnJ7+r9lLLbxgjKG6z83G11ouOJ?= =?us-ascii?Q?bPteWWTJMzumFg5GxPPhSNOOVBC4wip2FTMOjOpqiXHlRxq3RGyD4U5sjVAq?= =?us-ascii?Q?WwXKis2Nq51G0rQaQIxBVvwpQu5qv0v/lj4s3iEau4KKMRvNiRrHLRAGSENv?= =?us-ascii?Q?4rnSEETfWJ9hebwHOPCfRgznHaq9OPJPcZqmyfCvaY200ljMVh9ZY8komp/v?= =?us-ascii?Q?3GaXRg=3D=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:satlexmb07.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(1800799024)(82310400026)(376014)(36860700013); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jan 2026 20:08:08.3794 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 228608a4-dcc7-4d60-563f-08de5d169fcc X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001E9.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4136 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" Need to make sure gfxoff is disallowed when we touch GC registers over MMIO. Cc: Yifan Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c index 4d5c6bdd8cad7..d5ca57b670cd0 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c @@ -4787,6 +4787,7 @@ static int gfx_v12_0_set_eop_interrupt_state(struct amdgpu_device *adev, unsigned type, enum amdgpu_interrupt_state state) { + amdgpu_gfx_off_ctrl(adev, false); switch (type) { case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: gfx_v12_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); @@ -4809,6 +4810,8 @@ static int gfx_v12_0_set_eop_interrupt_state(struct amdgpu_device *adev, default: break; } + amdgpu_gfx_off_ctrl(adev, true); + return 0; } @@ -4873,6 +4876,7 @@ static int gfx_v12_0_set_priv_reg_fault_state(struct amdgpu_device *adev, u32 cp_int_cntl_reg, cp_int_cntl; int i, j; + amdgpu_gfx_off_ctrl(adev, false); switch (state) { case AMDGPU_IRQ_STATE_DISABLE: case AMDGPU_IRQ_STATE_ENABLE: @@ -4907,6 +4911,7 @@ static int gfx_v12_0_set_priv_reg_fault_state(struct amdgpu_device *adev, default: break; } + amdgpu_gfx_off_ctrl(adev, true); return 0; } @@ -4919,6 +4924,7 @@ static int gfx_v12_0_set_bad_op_fault_state(struct amdgpu_device *adev, u32 cp_int_cntl_reg, cp_int_cntl; int i, j; + amdgpu_gfx_off_ctrl(adev, false); switch (state) { case AMDGPU_IRQ_STATE_DISABLE: case AMDGPU_IRQ_STATE_ENABLE: @@ -4953,6 +4959,8 @@ static int gfx_v12_0_set_bad_op_fault_state(struct amdgpu_device *adev, default: break; } + amdgpu_gfx_off_ctrl(adev, true); + return 0; } @@ -4964,6 +4972,7 @@ static int gfx_v12_0_set_priv_inst_fault_state(struct amdgpu_device *adev, u32 cp_int_cntl_reg, cp_int_cntl; int i, j; + amdgpu_gfx_off_ctrl(adev, false); switch (state) { case AMDGPU_IRQ_STATE_DISABLE: case AMDGPU_IRQ_STATE_ENABLE: @@ -4984,6 +4993,7 @@ static int gfx_v12_0_set_priv_inst_fault_state(struct amdgpu_device *adev, default: break; } + amdgpu_gfx_off_ctrl(adev, true); return 0; } -- 2.52.0