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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:satlexmb08.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(82310400026)(376014)(36860700013)(1800799024); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Jan 2026 01:59:21.9841 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: af99d3c7-add3-4305-17b2-08de5e10db06 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00021F6B.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5942 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" From: Peichen Huang [WHY] To correctly control external panel replay fsm. [HOW] 1. External panel replay is 1-A option only now. 2. Update cursor update and dirty rects commands for external panel replay support. 3. Add external panel replay support flag in dc. Reviewed-by: Robin Chen Signed-off-by: Peichen Huang Signed-off-by: Wayne Lin --- drivers/gpu/drm/amd/display/dc/core/dc.c | 19 +++++-- drivers/gpu/drm/amd/display/dc/dc.h | 1 + drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 15 ++++-- drivers/gpu/drm/amd/display/dc/dc_types.h | 2 +- .../dc/link/protocols/link_dp_panel_replay.c | 52 +++++++++++++++++++ 5 files changed, 80 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index cb85b7ac2697..4305691ba45e 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -3860,7 +3860,7 @@ void dc_dmub_update_dirty_rect(struct dc *dc, if (!dc_dmub_should_send_dirty_rect_cmd(dc, stream)) return; - if (!dc_get_edp_link_panel_inst(dc, stream->link, &panel_inst)) + if (!dc->config.frame_update_cmd_version2 && !dc_get_edp_link_panel_inst(dc, stream->link, &panel_inst)) return; memset(&cmd, 0x0, sizeof(cmd)); @@ -3880,7 +3880,11 @@ void dc_dmub_update_dirty_rect(struct dc *dc, if (srf_updates[i].surface->flip_immediate) continue; - update_dirty_rect->cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1; + if (dc->config.frame_update_cmd_version2) + update_dirty_rect->cmd_version = DMUB_CMD_CURSOR_UPDATE_VERSION_2; + else + update_dirty_rect->cmd_version = DMUB_CMD_CURSOR_UPDATE_VERSION_1; + update_dirty_rect->dirty_rect_count = flip_addr->dirty_rect_count; memcpy(update_dirty_rect->src_dirty_rects, flip_addr->dirty_rects, sizeof(flip_addr->dirty_rects)); @@ -3894,6 +3898,7 @@ void dc_dmub_update_dirty_rect(struct dc *dc, update_dirty_rect->panel_inst = panel_inst; update_dirty_rect->pipe_idx = j; + update_dirty_rect->otg_inst = pipe_ctx->stream_res.tg->inst; dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT); } } @@ -3916,7 +3921,7 @@ static void build_dmub_update_dirty_rect( if (!dc_dmub_should_send_dirty_rect_cmd(dc, stream)) return; - if (!dc_get_edp_link_panel_inst(dc, stream->link, &panel_inst)) + if (!dc->config.frame_update_cmd_version2 && !dc_get_edp_link_panel_inst(dc, stream->link, &panel_inst)) return; memset(&cmd, 0x0, sizeof(cmd)); @@ -3935,7 +3940,12 @@ static void build_dmub_update_dirty_rect( /* Do not send in immediate flip mode */ if (srf_updates[i].surface->flip_immediate) continue; - update_dirty_rect->cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1; + + if (dc->config.frame_update_cmd_version2) + update_dirty_rect->cmd_version = DMUB_CMD_CURSOR_UPDATE_VERSION_2; + else + update_dirty_rect->cmd_version = DMUB_CMD_CURSOR_UPDATE_VERSION_1; + update_dirty_rect->dirty_rect_count = flip_addr->dirty_rect_count; memcpy(update_dirty_rect->src_dirty_rects, flip_addr->dirty_rects, sizeof(flip_addr->dirty_rects)); @@ -3948,6 +3958,7 @@ static void build_dmub_update_dirty_rect( continue; update_dirty_rect->panel_inst = panel_inst; update_dirty_rect->pipe_idx = j; + update_dirty_rect->otg_inst = pipe_ctx->stream_res.tg->inst; dc_dmub_cmd[*dmub_cmd_count].dmub_cmd = cmd; dc_dmub_cmd[*dmub_cmd_count].wait_type = DM_DMUB_WAIT_TYPE_NO_WAIT; (*dmub_cmd_count)++; diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index ab19b6230945..ce2eceba2ab7 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -560,6 +560,7 @@ struct dc_config { bool enable_dpia_pre_training; bool unify_link_enc_assignment; bool enable_cursor_offload; + bool frame_update_cmd_version2; struct spl_sharpness_range dcn_sharpness_range; struct spl_sharpness_range dcn_override_sharpness_range; }; diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c index dc1b3f6c22c9..e4dd5ca70987 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c +++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c @@ -1034,12 +1034,19 @@ static void dc_build_cursor_update_payload0( struct pipe_ctx *pipe_ctx, uint8_t p_idx, struct dmub_cmd_update_cursor_payload0 *payload) { + struct dc *dc = pipe_ctx->stream->ctx->dc; struct hubp *hubp = pipe_ctx->plane_res.hubp; unsigned int panel_inst = 0; - if (!dc_get_edp_link_panel_inst(hubp->ctx->dc, - pipe_ctx->stream->link, &panel_inst)) - return; + if (dc->config.frame_update_cmd_version2 == true) { + /* Don't need panel_inst for command version2 */ + payload->cmd_version = DMUB_CMD_CURSOR_UPDATE_VERSION_2; + } else { + if (!dc_get_edp_link_panel_inst(hubp->ctx->dc, + pipe_ctx->stream->link, &panel_inst)) + return; + payload->cmd_version = DMUB_CMD_CURSOR_UPDATE_VERSION_1; + } /* Payload: Cursor Rect is built from position & attribute * x & y are obtained from postion @@ -1052,8 +1059,8 @@ static void dc_build_cursor_update_payload0( payload->enable = hubp->pos.cur_ctl.bits.cur_enable; payload->pipe_idx = p_idx; - payload->cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1; payload->panel_inst = panel_inst; + payload->otg_inst = pipe_ctx->stream_res.tg->inst; } static void dc_build_cursor_position_update_payload0( diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h index 0e953059ff6d..2e38b6840c71 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_types.h @@ -1230,7 +1230,7 @@ struct replay_settings { uint32_t replay_desync_error_fail_count; /* The frame skip number dal send to DMUB */ uint16_t frame_skip_number; - /* Current Panel Replay event */ + /* Current Panel Replay events */ uint32_t replay_events; }; diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c index bbd6f93f5c98..cc3b44cf7662 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c @@ -35,6 +35,46 @@ #define DP_SINK_PR_ENABLE_AND_CONFIGURATION 0x37B +static unsigned int dp_pr_calc_num_static_frames(unsigned int vsync_rate_hz) +{ + // at least 2 frames for static screen + unsigned int num_frames = 2; + + // get number of frames for at least 50ms + if (vsync_rate_hz > 40) + num_frames = (vsync_rate_hz + 10) / 20; + + return num_frames; +} + +static void dp_pr_set_static_screen_param(struct dc_link *link) +{ + struct dc_static_screen_params params = {0}; + struct dc *dc = link->ctx->dc; + // only support DP sst for now + if (!dc_is_dp_sst_signal(link->connector_signal)) + return; + + for (int i = 0; i < MAX_PIPES; i++) { + if (dc->current_state->res_ctx.pipe_ctx[i].stream && + dc->current_state->res_ctx.pipe_ctx[i].stream->link == link) { + struct dc_stream_state *stream = dc->current_state->res_ctx.pipe_ctx[i].stream; + unsigned int vsync_rate_hz = div64_u64(div64_u64( + (stream->timing.pix_clk_100hz * (u64)100), + stream->timing.v_total), + stream->timing.h_total); + + params.triggers.cursor_update = true; + params.triggers.overlay_update = true; + params.triggers.surface_update = true; + params.num_frames = dp_pr_calc_num_static_frames(vsync_rate_hz); + + dc_stream_set_static_screen_params(dc, &stream, 1, ¶ms); + break; + } + } +} + static bool dp_setup_panel_replay(struct dc_link *link, const struct dc_stream_state *stream) { /* To-do: Setup Replay */ @@ -159,6 +199,9 @@ bool dp_pr_get_panel_inst(const struct dc *dc, if (!dc || !link || !inst_out) return false; + if (dc->config.frame_update_cmd_version2 == false) + return dc_get_edp_link_panel_inst(dc, link, inst_out); + if (!dc_is_dp_sst_signal(link->connector_signal)) /* only supoprt DP sst (eDP included) for now */ return false; @@ -199,6 +242,9 @@ bool dp_pr_enable(struct dc_link *link, bool enable) if (!dp_pr_get_panel_inst(dc, link, &panel_inst)) return false; + if (enable && !dc_is_embedded_signal(link->connector_signal)) + dp_pr_set_static_screen_param(link); + if (link->replay_settings.replay_allow_active != enable) { //for sending PR enable commands to DMUB memset(&cmd, 0, sizeof(cmd)); @@ -276,6 +322,12 @@ bool dp_pr_copy_settings(struct dc_link *link, struct replay_context *replay_con pipe_ctx->stream->timing.v_border_top + pipe_ctx->stream->timing.v_border_bottom) / pipe_ctx->stream->timing.dsc_cfg.num_slices_v; + if (dc_is_embedded_signal(link->connector_signal)) + cmd.pr_copy_settings.data.main_link_activity_option = 0x03;//OPTION_1C; + else + // For external DP, use option 1-A + cmd.pr_copy_settings.data.main_link_activity_option = 0x01;//OPTION_1A; + dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); return true; } -- 2.43.0