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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:satlexmb08.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(1800799024)(36860700013)(82310400026)(376014); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Jan 2026 11:00:00.6505 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6c6d5da9-6287-42d6-49a9-08de5e5c61fe X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF0000343F.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6064 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" Implement the AMDGPU_USERQ_OP_MODIFY ioctl operation to enable runtime updates of compute queues. v2: move queue size validate to a separate patch remove the check for AMDGPU_HW_IP_COMPUTE (Alex) Suggested-by: Alex Deucher Signed-off-by: Jesse Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 61 +++++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h | 3 ++ include/uapi/drm/amdgpu_drm.h | 1 + 3 files changed, 65 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c index 256ceca6d429..3003aba22e1d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c @@ -837,6 +837,7 @@ static int amdgpu_userq_input_args_validate(struct drm_device *dev, switch (args->in.op) { case AMDGPU_USERQ_OP_CREATE: + case AMDGPU_USERQ_OP_MODIFY: if (args->in.flags & ~(AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_MASK | AMDGPU_USERQ_CREATE_FLAGS_QUEUE_SECURE)) return -EINVAL; @@ -901,6 +902,60 @@ bool amdgpu_userq_enabled(struct drm_device *dev) return false; } +static int amdgpu_modify_queue(struct drm_file *filp, union drm_amdgpu_userq *args) +{ + struct amdgpu_fpriv *fpriv = filp->driver_priv; + struct amdgpu_userq_mgr *uq_mgr = &fpriv->userq_mgr; + struct amdgpu_device *adev = uq_mgr->adev; + struct amdgpu_usermode_queue *queue; + const struct amdgpu_userq_funcs *userq_funcs; + int r; + + mutex_lock(&uq_mgr->userq_mutex); + queue = amdgpu_userq_find(uq_mgr, args->in.queue_id); + if (!queue) { + drm_file_err(uq_mgr->file, "Queue %u not found\n", args->in.queue_id); + r = -EINVAL; + goto unlock; + } + + userq_funcs = adev->userq_funcs[queue->queue_type]; + + /* + * Unmap the queue if it's mapped or preempted to ensure a clean update. + * If the queue is already unmapped or hung, we skip this step. + */ + if (queue->state == AMDGPU_USERQ_STATE_MAPPED || + queue->state == AMDGPU_USERQ_STATE_PREEMPTED) { + r = amdgpu_userq_unmap_helper(queue); + if (r) { + drm_file_err(uq_mgr->file, "Failed to unmap queue %llu\n", + queue->doorbell_index); + goto unlock; + } + } + + r = userq_funcs->mqd_update(queue, &args->in); + if (r) + goto unlock; + /* + * If the queue is considered active (has valid size, address, and percentage), + * we attempt to map it. This effectively starts the queue or restarts it + * if it was previously running. + */ + if (AMDGPU_USERQ_IS_ACTIVE(queue)) { + r = amdgpu_userq_map_helper(queue); + if (r) + drm_file_err(uq_mgr->file, "Failed to remap queue %llu after update\n", + queue->doorbell_index); + } + +unlock: + mutex_unlock(&uq_mgr->userq_mutex); + + return r; +} + int amdgpu_userq_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) { @@ -920,6 +975,12 @@ int amdgpu_userq_ioctl(struct drm_device *dev, void *data, drm_file_err(filp, "Failed to create usermode queue\n"); break; + + case AMDGPU_USERQ_OP_MODIFY: + r = amdgpu_modify_queue(filp, args); + if (r) + drm_file_err(filp, "Failed to modify usermode queue\n"); + break; case AMDGPU_USERQ_OP_FREE: r = amdgpu_userq_destroy(filp, args->in.queue_id); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h index 833468b58603..7cd1ea94e368 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h @@ -31,6 +31,9 @@ #define to_ev_fence(f) container_of(f, struct amdgpu_eviction_fence, base) #define uq_mgr_to_fpriv(u) container_of(u, struct amdgpu_fpriv, userq_mgr) #define work_to_uq_mgr(w, name) container_of(w, struct amdgpu_userq_mgr, name) +#define AMDGPU_USERQ_IS_ACTIVE(q) ((q)->userq_prop->queue_size > 0 && \ + (q)->userq_prop->hqd_base_gpu_addr != 0 && \ + (q)->userq_prop->queue_percentage > 0) enum amdgpu_userq_state { AMDGPU_USERQ_STATE_UNMAPPED = 0, diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index c52949ea8c1e..aa9b31578c6b 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -330,6 +330,7 @@ union drm_amdgpu_ctx { /* user queue IOCTL operations */ #define AMDGPU_USERQ_OP_CREATE 1 #define AMDGPU_USERQ_OP_FREE 2 +#define AMDGPU_USERQ_OP_MODIFY 3 /* queue priority levels */ /* low < normal low < normal high < high */ -- 2.49.0