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Wed, 11 Feb 2026 19:09:53 -0600 From: To: CC: Alex Deucher , Harry Wentland , Pratik Vishwakarma , Aurabindo Pillai , Ivan Lipski , Alex Hung , Roman Li Subject: [PATCH 0/7] Patch set to support dcn42 Date: Wed, 11 Feb 2026 20:09:42 -0500 Message-ID: <20260212010949.654686-1-Roman.Li@amd.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF00000013:EE_|SJ5PPF0C60B25BF:EE_ X-MS-Office365-Filtering-Correlation-Id: 02c0de03-a731-418c-aa07-08de69d36e03 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|376014|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?R6VJTmTrbx98akyULt4n+jTWWV/usdAWVWejovOC/y5ovYaQhOjxlOAvce9F?= =?us-ascii?Q?7Po7e/THq4O3tOt5LEgtLuWZfnamHFrjEwi6llF+QCukIBF0cL5++HFDVVkJ?= =?us-ascii?Q?15IFqfvYSMydVPr1Ex8LQf/M9GpnUM+PfaVb5+vfkPyiQToGdi1RcuKU2Cj0?= =?us-ascii?Q?pAoZrldp9xj0VfAsktnBAgUgWA6VmYaYsoTjXkKY0GFcR2snJDmpKW7S5rdy?= =?us-ascii?Q?FZiqIfktyILr4hBAAG4184RTjh63wXl16wXJTpS0YOwwEU4ODbk0HDY+55nT?= =?us-ascii?Q?pOoyWR//fCqaPAnOP+mWlw8Lt6vsB3jMknBI+yusgQK8zr82jHWosu2XjMmC?= =?us-ascii?Q?CabGrHMunGdlKQkjqf79go9TNsXsqFLwigvBzfGJYmBL9qP9dsN0JNOEhaYm?= =?us-ascii?Q?+l5S24bS30MB92kBoI61txmeBAoe6U7CMO6aH5m7503tk2+CmQzLBfT4g1oK?= =?us-ascii?Q?xOZfdL2/aMGmNVzETGKDMoSKT4LQEqPBrDe3LHMSdWUCxND1aBYS1UlJ4Ubs?= =?us-ascii?Q?E3B5A46yKF1+T49xOnxj2WoXoW7RNsGS2CU+Uw+N18IrcrPQbc77WiN7HWT4?= =?us-ascii?Q?VWUV3fgNMk2WGPiVhVbk33TJUXEh3du0hna4dNKSO2aKCemjFotHeiycj9IX?= =?us-ascii?Q?5unLkCoogFPHKPWnuu9deK+rXTW9qyZ18PClqetsEiSngiSGktcIBE7FYru4?= =?us-ascii?Q?hpvrCee9yGZYRBkudBjJvL0wzGRaF/aYGHphO0RZFmb/1LBJ7SpT60Ca+Hei?= =?us-ascii?Q?xKfahVICnG+PCvmrJygDvImazAqmIfeHA7LZLEEex0J8r6t+yVLUch3QzXT9?= =?us-ascii?Q?20U+cLOaJGSe5C3T1ATGLPaRazjqnRn9YiJB6W/+/BcN95yc5PCS72y3HBdu?= =?us-ascii?Q?Sirvtyn4EZbOy5zTt9ik4lkVMIPA0pDQKcxpxIEM0BOzEM4ZvDwKjgT2k2dV?= =?us-ascii?Q?0Mx02/N4PwPE6r84nZrBzBgam8XPT86n4cZ7TrY+IGRMre18lUsnHtOXJOvG?= =?us-ascii?Q?g8kZxyrthKqnpTqOR3/qEDYtpjOflkLnKXfTIisNglbZVkQvt4N+daIxxE3F?= =?us-ascii?Q?li7lO99Utx984vHqTKEk3ZM/bq8SiMkd6Th5ID+H/vNUa6ApRVXKPxkLUuaN?= =?us-ascii?Q?jcvX5Ao1JjFtNHZFShYdFyMpUx10HjbNdgUVeJigKJoVVJvnbHnW6SqXDoXZ?= =?us-ascii?Q?ZZfj/80Iru2tWBQp6ulUNVnH5FUMVR6Ede730WCrIxgENQhl0w8W5GO4DAIu?= =?us-ascii?Q?tpBT8ghswjqXmzpNzz6VEVKQImTDE1UjOq65MGvva+N2gRBzibYyP2joB1Qm?= =?us-ascii?Q?jlzQ+uXeJELd3RH/jxb0MOmCgg+rpy+1ALplC7IOKlHTIEGTbuys2YwoZnDi?= =?us-ascii?Q?/6lqlBopTCEG2Rfl036rM6y2ESP9Q22xpfSbr2XcGHuVbc/IqmEfV1yE9BR2?= =?us-ascii?Q?bi4xEUfYctoJaVWMaZwCW+3csEFBh67KXJNL/KA7wp8Cq3IjbX6L1L22nU8O?= =?us-ascii?Q?KTthBphCAbgqx/88qEpQ5QFUk8+UhWRsSC1ucg/yDz0sB2qcNWRgI3gyAb+4?= =?us-ascii?Q?cg9m1HXmS8NniMdPCoWuXKRb0BksykkmVwaUIQF3Iuj7gleen01rL6TtupTa?= =?us-ascii?Q?b7sb4PBoszMgRaQihhYr41mS4Nbn0Ju0mU0Szzr36AjddSZRzOmCG6Xo0Yl8?= =?us-ascii?Q?R3nGMw=3D=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17; 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Ip=[165.204.84.17]; Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF00000013.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ5PPF0C60B25BF X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" From: Roman Li This series adds initial support for DCN 4.2. Roman Li (7): drm/amd/display: Add dcn42 version identifiers drm/amd/display: Add dcn42 register headers drm/amd/display: Add dcn42 DC resources drm/amd/display: Add DMUB support for dcn42 drm/amd/display: Enable dcn42 DMUB drm/amd/display: Enable dcn42 DC drm/amd/display: Enable dcn42 in DM .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 41 +- .../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 3 +- .../display/dc/bios/command_table_helper2.c | 1 + .../gpu/drm/amd/display/dc/clk_mgr/Makefile | 11 +- .../display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c | 1152 + .../display/dc/clk_mgr/dcn42/dcn42_clk_mgr.h | 79 + .../amd/display/dc/clk_mgr/dcn42/dcn42_smu.c | 431 + .../amd/display/dc/clk_mgr/dcn42/dcn42_smu.h | 190 + .../drm/amd/display/dc/core/dc_hw_sequencer.c | 39 +- .../gpu/drm/amd/display/dc/core/dc_resource.c | 7 + drivers/gpu/drm/amd/display/dc/dc.h | 10 +- drivers/gpu/drm/amd/display/dc/dc_helper.c | 2 + drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 73 + drivers/gpu/drm/amd/display/dc/dc_types.h | 6 +- drivers/gpu/drm/amd/display/dc/dccg/Makefile | 11 +- .../amd/display/dc/dccg/dcn20/dcn20_dccg.h | 15 +- .../amd/display/dc/dccg/dcn42/dcn42_dccg.c | 278 + .../amd/display/dc/dccg/dcn42/dcn42_dccg.h | 263 + drivers/gpu/drm/amd/display/dc/dce/dce_abm.h | 60 +- drivers/gpu/drm/amd/display/dc/dio/Makefile | 11 +- .../dc/dio/dcn10/dcn10_stream_encoder.h | 10 +- .../dc/dio/dcn42/dcn42_dio_link_encoder.c | 205 + .../dc/dio/dcn42/dcn42_dio_link_encoder.h | 140 + .../dc/dio/dcn42/dcn42_dio_stream_encoder.c | 522 + .../dc/dio/dcn42/dcn42_dio_stream_encoder.h | 206 + drivers/gpu/drm/amd/display/dc/dpp/Makefile | 10 +- .../amd/display/dc/dpp/dcn401/dcn401_dpp.h | 5 +- .../drm/amd/display/dc/dpp/dcn42/dcn42_dpp.c | 338 + .../drm/amd/display/dc/dpp/dcn42/dcn42_dpp.h | 469 + drivers/gpu/drm/amd/display/dc/gpio/Makefile | 13 +- .../display/dc/gpio/dcn42/hw_factory_dcn42.c | 254 + .../display/dc/gpio/dcn42/hw_factory_dcn42.h | 31 + .../dc/gpio/dcn42/hw_translate_dcn42.c | 205 + .../dc/gpio/dcn42/hw_translate_dcn42.h | 36 + .../gpu/drm/amd/display/dc/gpio/hw_factory.c | 4 + .../drm/amd/display/dc/gpio/hw_translate.c | 4 + drivers/gpu/drm/amd/display/dc/hpo/Makefile | 11 +- .../hpo/dcn31/dcn31_hpo_dp_stream_encoder.h | 10 +- .../dc/hpo/dcn42/dcn42_hpo_dp_link_encoder.c | 93 + .../dc/hpo/dcn42/dcn42_hpo_dp_link_encoder.h | 17 + .../gpu/drm/amd/display/dc/hubbub/Makefile | 10 +- .../display/dc/hubbub/dcn10/dcn10_hubbub.h | 6 +- .../display/dc/hubbub/dcn42/dcn42_hubbub.c | 539 + .../display/dc/hubbub/dcn42/dcn42_hubbub.h | 268 + drivers/gpu/drm/amd/display/dc/hubp/Makefile | 10 +- .../amd/display/dc/hubp/dcn20/dcn20_hubp.h | 8 +- .../amd/display/dc/hubp/dcn42/dcn42_hubp.c | 643 + .../amd/display/dc/hubp/dcn42/dcn42_hubp.h | 79 + drivers/gpu/drm/amd/display/dc/hwss/Makefile | 12 +- .../drm/amd/display/dc/hwss/dce/dce_hwseq.h | 13 +- .../amd/display/dc/hwss/dcn42/dcn42_hwseq.c | 1476 + .../amd/display/dc/hwss/dcn42/dcn42_hwseq.h | 53 + .../amd/display/dc/hwss/dcn42/dcn42_init.c | 167 + .../amd/display/dc/hwss/dcn42/dcn42_init.h | 11 + .../drm/amd/display/dc/hwss/hw_sequencer.h | 17 +- .../display/dc/hwss/hw_sequencer_private.h | 5 +- .../gpu/drm/amd/display/dc/inc/hw/clk_mgr.h | 24 +- .../amd/display/dc/inc/hw/clk_mgr_internal.h | 42 +- drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h | 10 +- drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h | 20 +- .../amd/display/dc/inc/hw/timing_generator.h | 4 +- drivers/gpu/drm/amd/display/dc/irq/Makefile | 9 + .../display/dc/irq/dcn42/irq_service_dcn42.c | 412 + .../display/dc/irq/dcn42/irq_service_dcn42.h | 15 + .../gpu/drm/amd/display/dc/mmhubbub/Makefile | 10 +- .../dc/mmhubbub/dcn42/dcn42_mmhubbub.c | 25 + .../dc/mmhubbub/dcn42/dcn42_mmhubbub.h | 13 + drivers/gpu/drm/amd/display/dc/mpc/Makefile | 10 +- .../amd/display/dc/mpc/dcn401/dcn401_mpc.c | 13 +- .../amd/display/dc/mpc/dcn401/dcn401_mpc.h | 10 +- .../drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c | 1121 + .../drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h | 1006 + drivers/gpu/drm/amd/display/dc/optc/Makefile | 10 +- .../amd/display/dc/optc/dcn10/dcn10_optc.h | 20 +- .../amd/display/dc/optc/dcn42/dcn42_optc.c | 198 + .../amd/display/dc/optc/dcn42/dcn42_optc.h | 211 + drivers/gpu/drm/amd/display/dc/pg/Makefile | 10 +- .../amd/display/dc/pg/dcn42/dcn42_pg_cntl.c | 648 + .../amd/display/dc/pg/dcn42/dcn42_pg_cntl.h | 175 + .../gpu/drm/amd/display/dc/resource/Makefile | 18 + .../dc/resource/dcn42/dcn42_resource.c | 2337 + .../dc/resource/dcn42/dcn42_resource.h | 588 + .../dc/resource/dcn42/dcn42_resource_fpu.c | 47 + .../dc/resource/dcn42/dcn42_resource_fpu.h | 33 + drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 5 +- drivers/gpu/drm/amd/display/dmub/src/Makefile | 3 +- .../gpu/drm/amd/display/dmub/src/dmub_dcn42.c | 752 + .../gpu/drm/amd/display/dmub/src/dmub_dcn42.h | 171 + .../gpu/drm/amd/display/dmub/src/dmub_srv.c | 64 +- .../gpu/drm/amd/display/include/dal_asic_id.h | 1 + .../gpu/drm/amd/display/include/dal_types.h | 1 + .../include/asic_reg/dcn/dcn_4_2_0_offset.h | 17872 ++++ .../include/asic_reg/dcn/dcn_4_2_0_sh_mask.h | 67277 ++++++++++++++++ .../include/asic_reg/dpcs/dpcs_4_0_0_offset.h | 142 + .../asic_reg/dpcs/dpcs_4_0_0_sh_mask.h | 688 + 95 files changed, 102551 insertions(+), 47 deletions(-) create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.h create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.h create mode 100644 drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c create mode 100644 drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.h create mode 100644 drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_link_encoder.c create mode 100644 drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_link_encoder.h create mode 100644 drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_stream_encoder.c create mode 100644 drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_stream_encoder.h create mode 100644 drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.c create mode 100644 drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.h create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dcn42/hw_factory_dcn42.c create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dcn42/hw_factory_dcn42.h create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dcn42/hw_translate_dcn42.c create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dcn42/hw_translate_dcn42.h create mode 100644 drivers/gpu/drm/amd/display/dc/hpo/dcn42/dcn42_hpo_dp_link_encoder.c create mode 100644 drivers/gpu/drm/amd/display/dc/hpo/dcn42/dcn42_hpo_dp_link_encoder.h create mode 100644 drivers/gpu/drm/amd/display/dc/hubbub/dcn42/dcn42_hubbub.c create mode 100644 drivers/gpu/drm/amd/display/dc/hubbub/dcn42/dcn42_hubbub.h create mode 100644 drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c create mode 100644 drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.h create mode 100644 drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c create mode 100644 drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.h create mode 100644 drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_init.c create mode 100644 drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_init.h create mode 100644 drivers/gpu/drm/amd/display/dc/irq/dcn42/irq_service_dcn42.c create mode 100644 drivers/gpu/drm/amd/display/dc/irq/dcn42/irq_service_dcn42.h create mode 100644 drivers/gpu/drm/amd/display/dc/mmhubbub/dcn42/dcn42_mmhubbub.c create mode 100644 drivers/gpu/drm/amd/display/dc/mmhubbub/dcn42/dcn42_mmhubbub.h create mode 100644 drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c create mode 100644 drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h create mode 100644 drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.c create mode 100644 drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.h create mode 100644 drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c create mode 100644 drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.h create mode 100644 drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c create mode 100644 drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h create mode 100644 drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.c create mode 100644 drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.h create mode 100644 drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c create mode 100644 drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_2_0_offset.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_2_0_sh_mask.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_4_0_0_offset.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_4_0_0_sh_mask.h -- 2.34.1