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Mon, 16 Feb 2026 15:13:50 -0600 From: Alex Deucher To: , CC: Alex Deucher , Jesse Zhang Subject: [PATCH 4/8] drm/amdgpu: require a job to schedule an IB Date: Mon, 16 Feb 2026 16:13:36 -0500 Message-ID: <20260216211340.16364-5-alexander.deucher@amd.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260216211340.16364-1-alexander.deucher@amd.com> References: <20260216211340.16364-1-alexander.deucher@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00001CEA:EE_|SJ1PR12MB6361:EE_ X-MS-Office365-Filtering-Correlation-Id: 5dbfba89-218b-47b4-0769-08de6da0495d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|82310400026|1800799024|376014|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?/PmFI5msJ57ZHle/9hoUndCVOEkuZ6bNjfkS5ld8FBs0Wij3cJcEpgotH7us?= =?us-ascii?Q?nQ2L4GcaBJjb6w/TxtMa+TCLE/6rH9KkRR7CiCOjL8cjbPb2mH1q9CLoZAMf?= =?us-ascii?Q?P2PTLMBm2Dfpma2q5F54fjhkUNEpiV6ICMxYInEdJET0NZQFsOkAX9jjBIbc?= =?us-ascii?Q?LGyKx4I9zgjhNxTUqJeBOtmg4BF/v9aWnslCGiR/IuHOeEPAd4YE2bGBtZ8Z?= =?us-ascii?Q?AQuRE05mmpNXVwYWkk1VusqV30wZu7xPjPTTLGmqJUalfYlvDkhjXWf2uj9s?= =?us-ascii?Q?YnlC2svxj8PficeGvCQcaM9cU8l66mmVQ0VK46mZ8gmInWXPK70U44QOy2hC?= =?us-ascii?Q?981m4UEPfvIDtpjjt5XvPFIooOmqTWjUIwGFg9eHvsyZ0hpFuBeiXt4lKBUi?= =?us-ascii?Q?W4+9e6+EPVY/aT/FcLCWWNIdfq3SAtwpLzLi1CA82brmXB+azrVsYbZJVzBn?= =?us-ascii?Q?wM1TJcZZQqmcTVHxnhhsLahd068dEvdkjY9bwF3AGmxgj0cWs1I3cPf//rJU?= =?us-ascii?Q?h+NyoR/k+ar3CC3bQ5aC9IYwHGXJOOYZo/BzK32ZvroFxxDVaQ1PL01y/B3W?= =?us-ascii?Q?SFH34dZg6WI20uT7+0wNnxQ+Gw06fYSoAf9U9+vl3zeNiOfeyxpkAJhK45kY?= =?us-ascii?Q?qkE+/buMAY4lDSZszs2zgHqrPPUJDHPo0mXQG8GGc1l78wp+u1TjIIiLiHay?= =?us-ascii?Q?vUVxMey75mwuX1M7HD/xmBUlMl5yyUQ66YCEqXJlJpEk71cNBA6VDuOMlfx3?= =?us-ascii?Q?tjAa4gLiOK4dNt8ZwLUnbY3hMXQ+NMv7sv8OOJa8Q0Hyxp62dKc5Yja70Aud?= =?us-ascii?Q?7rto+VOYhBpKDLFOsVnQStz//3JoBvWLyWqVHfb2pbQqzod/0g75o3JS1TiU?= =?us-ascii?Q?DAUB0fwWTz6Zxz5+v7S6qMkh/h16pYIAu9oMLOpMsK25JQTi2mZXKxyuRHNI?= =?us-ascii?Q?EI5b3RedqXy+s/A/iRFbtUCCg/934V24uVSbij63SN1Wd1JXdnr7RHjC8VqR?= =?us-ascii?Q?T7u3EJrE4hp3+LPcbzVQNIWGdMuaQ8CqZlj3okB0I0QyqxvyaoB9HO6wdvMk?= =?us-ascii?Q?4VyclRREeZCZQArATgTuVQ9pQIAKNZgNrUOhIYTvAbdbzFgmOIQoVsgE+86C?= =?us-ascii?Q?QaLREhRK2U9VbiBsFjzkbHgVBPZ8h24DHO2DJkRJQlS+EqRDjRSUGfjDDJIf?= =?us-ascii?Q?LV8B7242nvWNk2ePSkl9r5+UkD2iOntLOIYI/AhmTYDlY2WV/D5xB88UZDlN?= =?us-ascii?Q?hbtxxuGWltVKetbJhtAiazkYTNR0UFRzCF3kGQvyWH4p0kXCilrySg3hoYzU?= =?us-ascii?Q?UpKYOPuPkPs2pL8KXE8CcdQJCvta3dEQsj/f/ZLS9hZ2AZF1HCXbv7rXHn5R?= =?us-ascii?Q?r92oJqZfbAdi94I4VOI47a5UQa0uw7exWoyDlhKRELbOWTCe29QBkVoN+dFt?= =?us-ascii?Q?0fiB7Lw88GOqaSapIoVvRjefvanqIju5XyXFm244erSoY0as81oeHAn0pEyr?= =?us-ascii?Q?6nVVOz4YjBrcXagRP78ubpJsDcotb7gdegGUVdK7227aTLtmVCkPH74MgsnI?= =?us-ascii?Q?hQZUnh4dmFR7jSeXYwHyZIuQ6KzDsDSVKHfV5ymbySBDcnJLor/lNMSzkFSi?= =?us-ascii?Q?QinF8L4D2Fq44F8CzkVR0RvhpWtGyCbSL9zL8jxoRouRrIZQnmw9dpiLqT5y?= =?us-ascii?Q?xZEsWQ=3D=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17; 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Ip=[165.204.84.17]; Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CEA.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6361 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" Remove the old direct submit path. This simplifies the code. v2: remove more local variables Reviewed-by: Jesse Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 113 ++++++++------------- drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 5 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 3 +- 4 files changed, 45 insertions(+), 78 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c index 823b92005689a..4ec1058b7cdfa 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c @@ -685,7 +685,7 @@ int amdgpu_amdkfd_submit_ib(struct amdgpu_device *adev, job->vmid = vmid; job->num_ibs = 1; - ret = amdgpu_ib_schedule(ring, 1, ib, job, &f); + ret = amdgpu_ib_schedule(ring, job, &f); if (ret) { drm_err(adev_to_drm(adev), "failed to schedule IB.\n"); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c index 80565c4a31bdf..55a9670f1dd90 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c @@ -103,8 +103,6 @@ void amdgpu_ib_free(struct amdgpu_ib *ib, struct dma_fence *f) * amdgpu_ib_schedule - schedule an IB (Indirect Buffer) on the ring * * @ring: ring index the IB is associated with - * @num_ibs: number of IBs to schedule - * @ibs: IB objects to schedule * @job: job to schedule * @f: fence created during this submission * @@ -121,90 +119,70 @@ void amdgpu_ib_free(struct amdgpu_ib *ib, struct dma_fence *f) * a CONST_IB), it will be put on the ring prior to the DE IB. Prior * to SI there was just a DE IB. */ -int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs, - struct amdgpu_ib *ibs, struct amdgpu_job *job, +int amdgpu_ib_schedule(struct amdgpu_ring *ring, struct amdgpu_job *job, struct dma_fence **f) { struct amdgpu_device *adev = ring->adev; - struct amdgpu_ib *ib = &ibs[0]; + struct amdgpu_ib *ib; struct dma_fence *tmp = NULL; struct amdgpu_fence *af; struct amdgpu_fence *vm_af; bool need_ctx_switch; - struct amdgpu_vm *vm; uint64_t fence_ctx; uint32_t status = 0, alloc_size; unsigned int fence_flags = 0; - bool secure, init_shadow; - u64 shadow_va, csa_va, gds_va; + bool secure; int vmid = AMDGPU_JOB_GET_VMID(job); bool need_pipe_sync = false; unsigned int cond_exec; unsigned int i; int r = 0; - if (num_ibs == 0) + if (!job) + return -EINVAL; + if (job->num_ibs == 0) return -EINVAL; - /* ring tests don't use a job */ - if (job) { - vm = job->vm; - fence_ctx = job->base.s_fence ? - job->base.s_fence->finished.context : 0; - shadow_va = job->shadow_va; - csa_va = job->csa_va; - gds_va = job->gds_va; - init_shadow = job->init_shadow; - af = job->hw_fence; - /* Save the context of the job for reset handling. - * The driver needs this so it can skip the ring - * contents for guilty contexts. - */ - af->context = fence_ctx; - /* the vm fence is also part of the job's context */ - job->hw_vm_fence->context = fence_ctx; - } else { - vm = NULL; - fence_ctx = 0; - shadow_va = 0; - csa_va = 0; - gds_va = 0; - init_shadow = false; - af = kzalloc(sizeof(*af), GFP_ATOMIC); - if (!af) - return -ENOMEM; - } + ib = &job->ibs[0]; + fence_ctx = job->base.s_fence ? + job->base.s_fence->finished.context : 0; + af = job->hw_fence; + vm_af = job->hw_vm_fence; + /* Save the context of the job for reset handling. + * The driver needs this so it can skip the ring + * contents for guilty contexts. + */ + af->context = fence_ctx; + /* the vm fence is also part of the job's context */ + vm_af->context = fence_ctx; if (!ring->sched.ready) { dev_err(adev->dev, "couldn't schedule ib on ring <%s>\n", ring->name); - r = -EINVAL; - goto free_fence; + return -EINVAL; } - if (vm && !job->vmid) { + if (job->vm && !job->vmid) { dev_err(adev->dev, "VM IB without ID\n"); - r = -EINVAL; - goto free_fence; + return -EINVAL; } if ((ib->flags & AMDGPU_IB_FLAGS_SECURE) && (!ring->funcs->secure_submission_supported)) { dev_err(adev->dev, "secure submissions not supported on ring <%s>\n", ring->name); - r = -EINVAL; - goto free_fence; + return -EINVAL; } - alloc_size = ring->funcs->emit_frame_size + num_ibs * + alloc_size = ring->funcs->emit_frame_size + job->num_ibs * ring->funcs->emit_ib_size; r = amdgpu_ring_alloc(ring, alloc_size); if (r) { dev_err(adev->dev, "scheduling IB failed (%d).\n", r); - goto free_fence; + return r; } need_ctx_switch = ring->current_ctx != fence_ctx; - if (ring->funcs->emit_pipeline_sync && job && + if (ring->funcs->emit_pipeline_sync && ((tmp = amdgpu_sync_get_fence(&job->explicit_sync)) || need_ctx_switch || amdgpu_vm_need_pipeline_sync(ring, job))) { @@ -216,14 +194,11 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs, dma_fence_put(tmp); } - if (job) { - vm_af = job->hw_vm_fence; - /* VM sequence */ - vm_af->ib_wptr = ring->wptr; - amdgpu_vm_flush(ring, job, need_pipe_sync); - vm_af->ib_dw_size = - amdgpu_ring_get_dw_distance(ring, vm_af->ib_wptr, ring->wptr); - } + /* VM sequence */ + vm_af->ib_wptr = ring->wptr; + amdgpu_vm_flush(ring, job, need_pipe_sync); + vm_af->ib_dw_size = + amdgpu_ring_get_dw_distance(ring, vm_af->ib_wptr, ring->wptr); /* IB sequence */ af->ib_wptr = ring->wptr; @@ -240,8 +215,8 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs, ring->funcs->emit_wave_limit(ring, true); if (ring->funcs->emit_gfx_shadow && adev->gfx.cp_gfx_shadow) - amdgpu_ring_emit_gfx_shadow(ring, shadow_va, csa_va, gds_va, - init_shadow, vmid); + amdgpu_ring_emit_gfx_shadow(ring, job->shadow_va, job->csa_va, job->gds_va, + job->init_shadow, vmid); if (ring->funcs->init_cond_exec) cond_exec = amdgpu_ring_init_cond_exec(ring, @@ -255,7 +230,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs, if (need_ctx_switch) status |= AMDGPU_HAVE_CTX_SWITCH; - if (job && ring->funcs->emit_cntxcntl) { + if (ring->funcs->emit_cntxcntl) { status |= job->preamble_status; status |= job->preemption_status; amdgpu_ring_emit_cntxcntl(ring, status); @@ -264,15 +239,15 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs, /* Setup initial TMZiness and send it off. */ secure = false; - if (job && ring->funcs->emit_frame_cntl) { + if (ring->funcs->emit_frame_cntl) { secure = ib->flags & AMDGPU_IB_FLAGS_SECURE; amdgpu_ring_emit_frame_cntl(ring, true, secure); } - for (i = 0; i < num_ibs; ++i) { - ib = &ibs[i]; + for (i = 0; i < job->num_ibs; ++i) { + ib = &job->ibs[i]; - if (job && ring->funcs->emit_frame_cntl) { + if (ring->funcs->emit_frame_cntl) { if (secure != !!(ib->flags & AMDGPU_IB_FLAGS_SECURE)) { amdgpu_ring_emit_frame_cntl(ring, false, secure); secure = !secure; @@ -284,7 +259,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs, status &= ~AMDGPU_HAVE_CTX_SWITCH; } - if (job && ring->funcs->emit_frame_cntl) + if (ring->funcs->emit_frame_cntl) amdgpu_ring_emit_frame_cntl(ring, false, secure); amdgpu_device_invalidate_hdp(adev, ring); @@ -296,7 +271,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs, fence_flags |= AMDGPU_FENCE_FLAG_TC_WB_ONLY; /* wrap the last IB with fence */ - if (job && job->uf_addr) { + if (job->uf_addr) { amdgpu_ring_emit_fence(ring, job->uf_addr, job->uf_sequence, fence_flags | AMDGPU_FENCE_FLAG_64BIT); } @@ -310,8 +285,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs, amdgpu_fence_emit(ring, af, fence_flags); *f = &af->base; /* get a ref for the job */ - if (job) - dma_fence_get(*f); + dma_fence_get(*f); if (ring->funcs->insert_end) ring->funcs->insert_end(ring); @@ -319,7 +293,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs, amdgpu_ring_patch_cond_exec(ring, cond_exec); ring->current_ctx = fence_ctx; - if (job && ring->funcs->emit_switch_buffer) + if (ring->funcs->emit_switch_buffer) amdgpu_ring_emit_switch_buffer(ring); if (ring->funcs->emit_wave_limit && @@ -333,11 +307,6 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs, amdgpu_ring_commit(ring); return 0; - -free_fence: - if (!job) - kfree(af); - return r; } /** diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c index 95aa87b4406eb..cd0707737a29b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c @@ -377,7 +377,7 @@ int amdgpu_job_submit_direct(struct amdgpu_job *job, struct amdgpu_ring *ring, int r; job->base.sched = &ring->sched; - r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs, job, fence); + r = amdgpu_ib_schedule(ring, job, fence); if (r) return r; @@ -447,8 +447,7 @@ static struct dma_fence *amdgpu_job_run(struct drm_sched_job *sched_job) dev_dbg(adev->dev, "Skip scheduling IBs in ring(%s)", ring->name); } else { - r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs, job, - &fence); + r = amdgpu_ib_schedule(ring, job, &fence); if (r) dev_err(adev->dev, "Error scheduling IBs (%d) in ring(%s)", r, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h index ce5af137ee400..fafb876d73da1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h @@ -575,8 +575,7 @@ int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, enum amdgpu_ib_pool_type pool, struct amdgpu_ib *ib); void amdgpu_ib_free(struct amdgpu_ib *ib, struct dma_fence *f); -int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, - struct amdgpu_ib *ibs, struct amdgpu_job *job, +int amdgpu_ib_schedule(struct amdgpu_ring *ring, struct amdgpu_job *job, struct dma_fence **f); int amdgpu_ib_pool_init(struct amdgpu_device *adev); void amdgpu_ib_pool_fini(struct amdgpu_device *adev); -- 2.53.0