From: Alex Hung <alex.hung@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: Harry Wentland <harry.wentland@amd.com>,
Leo Li <sunpeng.li@amd.com>,
Aurabindo Pillai <aurabindo.pillai@amd.com>,
Roman Li <roman.li@amd.com>, Wayne Lin <wayne.lin@amd.com>,
Tom Chung <chiahsuan.chung@amd.com>,
"Fangzhi Zuo" <jerry.zuo@amd.com>,
Dan Wheeler <daniel.wheeler@amd.com>, Ray Wu <Ray.Wu@amd.com>,
Ivan Lipski <ivan.lipski@amd.com>, Alex Hung <alex.hung@amd.com>
Subject: [PATCH 7/8] drm/amd/display: Prevent integer overflow when mhz to khz
Date: Wed, 25 Feb 2026 16:57:46 -0700 [thread overview]
Message-ID: <20260226000048.68030-8-alex.hung@amd.com> (raw)
In-Reply-To: <20260226000048.68030-1-alex.hung@amd.com>
[WHAT]
Cast to long long before multiplication to prevent overflow
when converting mhz to khz by multiplying by 1000.
This is reported as INTEGER_OVERFLOW errors by Coverity.
Reviewed-by: Roman Li <roman.li@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
---
.../drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c | 14 +++++++-------
.../drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c | 12 ++++++------
2 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c
index 604d256cb47a..9d8f81c3d3f0 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c
@@ -204,7 +204,7 @@ int dcn35_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispcl
khz_to_mhz_ceil(requested_dispclk_khz));
smu_print("requested_dispclk_khz = %d, actual_dispclk_set_mhz: %d\n", requested_dispclk_khz, actual_dispclk_set_mhz);
- return actual_dispclk_set_mhz * 1000;
+ return (int)((long long)actual_dispclk_set_mhz * 1000);
}
int dcn35_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr)
@@ -221,7 +221,7 @@ int dcn35_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr)
/* TODO: add code for programing DP DTO, currently this is down by command table */
- return actual_dprefclk_set_mhz * 1000;
+ return (int)((long long)actual_dprefclk_set_mhz * 1000);
}
int dcn35_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz)
@@ -238,7 +238,7 @@ int dcn35_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requeste
smu_print("requested_dcfclk_khz = %d, actual_dcfclk_set_mhz: %d\n", requested_dcfclk_khz, actual_dcfclk_set_mhz);
- return actual_dcfclk_set_mhz * 1000;
+ return (int)((long long)actual_dcfclk_set_mhz * 1000);
}
int dcn35_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz)
@@ -255,7 +255,7 @@ int dcn35_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int re
smu_print("requested_min_ds_dcfclk_khz = %d, actual_min_ds_dcfclk_mhz: %d\n", requested_min_ds_dcfclk_khz, actual_min_ds_dcfclk_mhz);
- return actual_min_ds_dcfclk_mhz * 1000;
+ return (int)((long long)actual_min_ds_dcfclk_mhz * 1000);
}
int dcn35_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz)
@@ -272,7 +272,7 @@ int dcn35_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz
smu_print("requested_dpp_khz = %d, actual_dppclk_set_mhz: %d\n", requested_dpp_khz, actual_dppclk_set_mhz);
- return actual_dppclk_set_mhz * 1000;
+ return (int)((long long)actual_dppclk_set_mhz * 1000);
}
void dcn35_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info)
@@ -424,7 +424,7 @@ int dcn35_smu_get_dprefclk(struct clk_mgr_internal *clk_mgr)
0);
smu_print("%s: SMU DPREF clk = %d mhz\n", __func__, dprefclk);
- return dprefclk * 1000;
+ return (int)((long long)dprefclk * 1000);
}
int dcn35_smu_get_dtbclk(struct clk_mgr_internal *clk_mgr)
@@ -439,7 +439,7 @@ int dcn35_smu_get_dtbclk(struct clk_mgr_internal *clk_mgr)
0);
smu_print("%s: get_dtbclk = %dmhz\n", __func__, dtbclk);
- return dtbclk * 1000;
+ return (int)((long long)dtbclk * 1000);
}
/* Arg = 1: Turn DTB on; 0: Turn DTB CLK OFF. when it is on, it is 600MHZ */
void dcn35_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c
index d3cc624cd758..c791bb1edb47 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c
@@ -193,7 +193,7 @@ int dcn42_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispcl
smu_print("requested_dispclk_khz = %d, actual_dispclk_set_mhz: %d\n",
requested_dispclk_khz, actual_dispclk_set_mhz);
- return actual_dispclk_set_mhz * 1000;
+ return (int)((long long)actual_dispclk_set_mhz * 1000);
}
@@ -212,7 +212,7 @@ int dcn42_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requeste
smu_print("requested_dcfclk_khz = %d, actual_dcfclk_set_mhz: %d\n",
requested_dcfclk_khz, actual_dcfclk_set_mhz);
- return actual_dcfclk_set_mhz * 1000;
+ return (int)((long long)actual_dcfclk_set_mhz * 1000);
}
int dcn42_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz)
@@ -230,7 +230,7 @@ int dcn42_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int re
smu_print("requested_min_ds_dcfclk_khz = %d, actual_min_ds_dcfclk_mhz: %d\n",
requested_min_ds_dcfclk_khz, actual_min_ds_dcfclk_mhz);
- return actual_min_ds_dcfclk_mhz * 1000;
+ return (int)((long long)actual_min_ds_dcfclk_mhz * 1000);
}
int dcn42_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz)
@@ -248,7 +248,7 @@ int dcn42_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz
smu_print("requested_dpp_khz = %d, actual_dppclk_set_mhz: %d\n",
requested_dpp_khz, actual_dppclk_set_mhz);
- return actual_dppclk_set_mhz * 1000;
+ return (int)((long long)actual_dppclk_set_mhz * 1000);
}
void dcn42_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info)
@@ -399,7 +399,7 @@ int dcn42_smu_get_dprefclk(struct clk_mgr_internal *clk_mgr)
0);
smu_print("%s: SMU DPREF clk = %d mhz\n", __func__, dprefclk);
- return dprefclk * 1000;
+ return (int)((long long)dprefclk * 1000);
}
int dcn42_smu_get_dtbclk(struct clk_mgr_internal *clk_mgr)
@@ -414,7 +414,7 @@ int dcn42_smu_get_dtbclk(struct clk_mgr_internal *clk_mgr)
0);
smu_print("%s: get_dtbclk = %dmhz\n", __func__, dtbclk);
- return dtbclk * 1000;
+ return (int)((long long)dtbclk * 1000);
}
/* Arg = 1: Turn DTB on; 0: Turn DTB CLK OFF. when it is on, it is 600MHZ */
void dcn42_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable)
--
2.43.0
next prev parent reply other threads:[~2026-02-26 0:03 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-02-25 23:57 [PATCH 0/8] DC Patches Feb 25, 2026 Alex Hung
2026-02-25 23:57 ` [PATCH 1/8] drm/amd/display: Skip cursor cache reset if hubp powergating is disabled Alex Hung
2026-02-25 23:57 ` [PATCH 2/8] drm/amd/display: Fallback to boot snapshot for dispclk Alex Hung
2026-02-25 23:57 ` [PATCH 3/8] drm/amd/display: Initialize replay_state to PR_STATE_INVALID Alex Hung
2026-02-25 23:57 ` [PATCH 4/8] drm/amd/display: Silence unused variable warning Alex Hung
2026-02-25 23:57 ` [PATCH 5/8] drm/amd/display: Remove redundant initializers Alex Hung
2026-02-25 23:57 ` [PATCH 6/8] drm/amd/display: Remove always-false branches Alex Hung
2026-02-25 23:57 ` Alex Hung [this message]
2026-02-25 23:57 ` [PATCH 8/8] drm/amd/display: Promote DC to 3.2.372 Alex Hung
2026-03-02 14:31 ` [PATCH 0/8] DC Patches Feb 25, 2026 Wheeler, Daniel
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